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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62856/comment/6edf4d2b_68e8f9db
PS5, Line 641: /
after a space Meera.
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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
Patch Set 5:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62856/comment/85bf7b48_50ec3f6d
PS1, Line 8:
> AIUI, UFS is the successor of eMMC
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/62856/comment/76ffca50_bbeb9ebe
PS2, Line 10: Enable UFS controller 1 UPD in fsp params.
> suggestion: […]
Done
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62856/comment/ea489c86_07477824
PS2, Line 620: /* UFS */
> That was quick, thanks Eric :) What do you think of the other comment I raised on chipset. […]
I will get back on this, Sheng. In discussion with FSP team as to why the array exists at the first place when we clearly have 1 controller. We could rename it if they would like to proceed with the array.
https://review.coreboot.org/c/coreboot/+/62856/comment/fa74818d_a329a9a6
PS2, Line 625: s_cfg->UfsEnable[1] = dev->enabled;
> I would also explicitly mark UFS UPD index 0 as `0` to make sure it's marked disable […]
Done
https://review.coreboot.org/c/coreboot/+/62856/comment/4128e937_6a530200
PS2, Line 622: if (!dev)
: s_cfg->UfsEnable[1] = 0;
: else
: s_cfg->UfsEnable[1] = dev->enabled;
:
> Or what I suggested in the other comment thread: […]
Ack
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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
soc/intel/alderlake: Add support for UFS controller
UFS (Universal Flash Storage) is the next generation storage
standard and a SCSI storage technology. It is also a successor
of eMMC.
Following changes are needed to add support for UFS in ADL-N.
1) Add UFS controller to chipset.cb and keep it off by default
2) Hook up FSP enable UPD for UFS #1 to the device from chipset.cb
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4
---
M src/soc/intel/alderlake/chipset.cb
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/62856/5
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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
soc/intel/alderlake: Add support for UFS controller
UFS (Universal Flash Storage) is the next generation storage
standard and a SCSI storage technology. It is also a successor
of eMMC.
Following changes are needed to add support for UFS in ADL-N.
1) Add UFS controller to chipset.cb and keep it off by default
2) Hook up FSP enable UPD for UFS #1 to the device from chipset.cb
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4
---
M src/soc/intel/alderlake/chipset.cb
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/62856/4
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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
soc/intel/alderlake: Add support for UFS controller
UFS (Universal Flash Storage) is the next generation storage
standard and a SCSI storage technology. It is also a successor
of eMMC.
Following changes are needed to add support for UFS in ADL-N.
1) Add UFS controller to chipset.cb and keep it off by default
2) Hook up FSP enable UPD for UFS #1 to the device from chipset.cb
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4
---
M src/soc/intel/alderlake/chipset.cb
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/62856/3
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63396 )
Change subject: Documentation: Add Dasharo to after-market firmware list
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File Documentation/distributions.md:
https://review.coreboot.org/c/coreboot/+/63396/comment/b066c8a4_fdd99108
PS2, Line 60: is open source
is an …
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Change subject: mb/google/brya/var/nereid: Enable pen garage
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Patch Set 1: Code-Review+1
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Change subject: soc/intel/alderlake: Add support to update descriptor at runtime
......................................................................
Patch Set 7:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63365/comment/99ca72a0_c56d4d60
PS7, Line 10: following
follow-up
File src/soc/intel/alderlake/bootblock/update_descriptor.c:
https://review.coreboot.org/c/coreboot/+/63365/comment/cb50f55c_1a93a495
PS7, Line 22: host(Flash Master 1)
Please add a space before the (.
https://review.coreboot.org/c/coreboot/+/63365/comment/9c84f560_e44069fc
PS7, Line 23: int
Use bool?
https://review.coreboot.org/c/coreboot/+/63365/comment/6f572354_caed0168
PS7, Line 27: BIOS_DEBUG
Should be an error?
https://review.coreboot.org/c/coreboot/+/63365/comment/7facda35_64874735
PS7, Line 33: printk(BIOS_DEBUG, "Host doesn't have write access to Descriptor Region\n");
Ditto.
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