coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/brya/var/nereid: Configure descriptor for Type-C / HDMI
by Reka Norman (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla. Hello Sam McNally, Reka Norman, build bot (Jenkins), Kangheui Won, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63366 to look at the new patch set (#6). Change subject: mb/google/brya/var/nereid: Configure descriptor for Type-C / HDMI ...................................................................... mb/google/brya/var/nereid: Configure descriptor for Type-C / HDMI Some bytes in the descriptor need to be set differently for Type-C and HDMI. To allow using a single firmware variant for both cases, update the descriptor at runtime based on fw_config. This is a temporary workaround while we find a better solution. The byte values were determined by changing the following CSE strap and comparing the generated descriptors: Type-C: TypeCPort2Config = "No Thunderbolt" HDMI: TypeCPort2Config = "DP Fixed Connection" BUG=b:226848617 TEST=Type-C and HDMI both work on nereid with fw_config set correctly. Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Signed-off-by: Reka Norman <rekanorman(a)google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/bootblock.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/brya/variants/nereid/Makefile.inc M src/mainboard/google/brya/variants/nereid/variant.c 5 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/63366/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Gerrit-Change-Number: 63366 Gerrit-PatchSet: 6 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add support to update descriptor at runtime
by Reka Norman (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Angel Pons. Hello Sam McNally, build bot (Jenkins), Reka Norman, Kangheui Won, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63365 to look at the new patch set (#6). Change subject: soc/intel/alderlake: Add support to update descriptor at runtime ...................................................................... soc/intel/alderlake: Add support to update descriptor at runtime On nereid, we need to update the descriptor based on fw_config (see the following patch), so add support to update the descriptor at runtime. This is a temporary workaround while we find a better solution. This is basically adding back the configure_pmc_descriptor() function removed in CB:63339, just making it generic and allowing it to update multiple bytes at once. BUG=b:226848617 TEST=With the following patch, Type-C and HDMI work on nereid. Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe Signed-off-by: Reka Norman <rekanorman(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/bootblock/update_descriptor.c M src/soc/intel/alderlake/include/soc/bootblock.h 4 files changed, 107 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/63365/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe Gerrit-Change-Number: 63365 Gerrit-PatchSet: 6 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power...
by Teddy Shih (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Henry Sun, Paul Menzel, Aseda Aboagye, Simon Yang, Karthik Ramasubramanian. Teddy Shih has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62776 ) Change subject: mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power consumption ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Dear All, Please kindly review my CL. Best Regards, Teddy -- To view, visit https://review.coreboot.org/c/coreboot/+/62776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79ec524c5ce8f2a79da4aeba084786fb9dac17af Gerrit-Change-Number: 62776 Gerrit-PatchSet: 3 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Super Ni <super.ni(a)intel.corp-partner.google.com> Gerrit-Reviewer: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Teddy Shih <teddyshihau(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jack Cheng <jack.cheng(a)ecs.corp-partner.google.com> Gerrit-CC: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 10:41:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/intelp2m: Add support for Alder Lake H macro generation
by Michał Kopeć (Code Review) 06 Apr '22

06 Apr '22

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63403 ) Change subject: util/intelp2m: Add support for Alder Lake H macro generation ...................................................................... util/intelp2m: Add support for Alder Lake H macro generation Add support for Alder Lake-H as a separate parsing profile, copying the existing 'Cannon' profile and adjusting for differences in reset mapping and GPIO macro generation. TEST=Generate GPIO macros for MSI PRO Z690-A Change-Id: I5871394bcb0636c2c803607ffb129441aa934417 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M util/intelp2m/config/config.go M util/intelp2m/description.md M util/intelp2m/main.go M util/intelp2m/parser/parser.go A util/intelp2m/platforms/adl_h/macro.go A util/intelp2m/platforms/adl_h/template.go 6 files changed, 251 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/63403/1 diff --git a/util/intelp2m/config/config.go b/util/intelp2m/config/config.go index 16fb4d6..bf82ef6 100644 --- a/util/intelp2m/config/config.go +++ b/util/intelp2m/config/config.go @@ -28,6 +28,7 @@ LewisburgType uint8 = 1 ApolloType uint8 = 2 CannonType uint8 = 3 + AlderHType uint8 = 4 ) var key uint8 = SunriseType @@ -36,7 +37,8 @@ "snr": SunriseType, "lbg": LewisburgType, "apl": ApolloType, - "cnl": CannonType} + "cnl": CannonType, + "adl_h": AlderHType} func PlatformSet(name string) int { if platformType, valid := platform[name]; valid { key = platformType @@ -62,6 +64,9 @@ func IsPlatformCannonLake() bool { return IsPlatform(CannonType) } +func IsPlatformAlderLakeH() bool { + return IsPlatform(AlderHType) +} var InputRegDumpFile *os.File = nil var OutputGenFile *os.File = nil diff --git a/util/intelp2m/description.md b/util/intelp2m/description.md index 1aaee40..0703941 100644 --- a/util/intelp2m/description.md +++ b/util/intelp2m/description.md @@ -36,6 +36,7 @@ lbg - Lewisburg PCH with Xeon SP CPU apl - Apollo Lake SoC cnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC + adl_h - AlderLake-H CPU (default "snr") (shell)$ ./intelp2m -p <platform> -file path/to/inteltool.log diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go index fdfc34f..eec5647 100644 --- a/util/intelp2m/main.go +++ b/util/intelp2m/main.go @@ -68,7 +68,8 @@ "\tsnr - Sunrise PCH or Skylake/Kaby Lake SoC\n"+ "\tlbg - Lewisburg PCH with Xeon SP\n"+ "\tapl - Apollo Lake SoC\n"+ - "\tcnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC\n") + "\tcnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC\n"+ + "\tadl_h - AlderLake-H CPU\n") fieldstyle := flag.String("fld", "none", "set fields macros style:\n"+ "\tcb - use coreboot style for bit fields macros\n"+ diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go index bfcdff8..c0918fe 100644 --- a/util/intelp2m/parser/parser.go +++ b/util/intelp2m/parser/parser.go @@ -10,6 +10,7 @@ "../platforms/lbg" "../platforms/apl" "../platforms/cnl" + "../platforms/adl_h" "../config" ) @@ -147,6 +148,9 @@ config.CannonType : cnl.PlatformSpecific{ InheritanceTemplate : snr.PlatformSpecific{}, }, + config.AlderHType : adl_h.PlatformSpecific{ + InheritanceTemplate : snr.PlatformSpecific{}, + }, } parser.platform = platform[config.PlatformGet()] } diff --git a/util/intelp2m/platforms/adl_h/macro.go b/util/intelp2m/platforms/adl_h/macro.go new file mode 100644 index 0000000..2a69557 --- /dev/null +++ b/util/intelp2m/platforms/adl_h/macro.go @@ -0,0 +1,213 @@ +package adl_h + +import ( + "strings" + "fmt" + "../common" + "../../config" + "../../fields" + "../snr" +) + +const ( + PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfc + PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff +) + +const ( + PAD_CFG_DW0 = common.PAD_CFG_DW0 + PAD_CFG_DW1 = common.PAD_CFG_DW1 + MAX_DW_NUM = common.MAX_DW_NUM +) + +type InheritanceMacro interface { + GpoMacroAdd() + NativeFunctionMacroAdd() + NoConnMacroAdd() +} + +type PlatformSpecific struct { + InheritanceMacro + InheritanceTemplate +} + +// RemmapRstSrc - remmap Pad Reset Source Config +func (PlatformSpecific) RemmapRstSrc() { + macro := common.GetMacro() + if config.TemplateGet() != config.TempInteltool { + // Use reset source remapping only if the input file is inteltool.log dump + return + } + if strings.Contains(macro.PadIdGet(), "GPD") { + // See reset map for the Alderlake GPD Group in the Community 2: + // https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/gp… + // remmap is not required because it is the same as common. + return + } + + dw0 := macro.Register(PAD_CFG_DW0) + var remapping = map[uint8]uint32{ + 0: common.RST_RSMRST << common.PadRstCfgShift, + 1: common.RST_DEEP << common.PadRstCfgShift, + 2: common.RST_PLTRST << common.PadRstCfgShift, + } + resetsrc, valid := remapping[dw0.GetResetConfig()] + if valid { + // dw0.SetResetConfig(resetsrc) + ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()] + dw0.ValueSet(ResetConfigFieldVal) + } else { + fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc ," ] for ", macro.PadIdGet()) + } + dw0.CntrMaskFieldsClear(common.PadRstCfgMask) +} + +// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro +// as a new argument +func (PlatformSpecific) Pull() { + macro := common.GetMacro() + dw1 := macro.Register(PAD_CFG_DW1) + var pull = map[uint8]string{ + 0x0: "NONE", + 0x2: "DN_5K", + 0x4: "DN_20K", + 0x9: "UP_1K", + 0xa: "UP_5K", + 0xb: "UP_2K", + 0xc: "UP_20K", + 0xd: "UP_667", + 0xf: "NATIVE", + } + str, valid := pull[dw1.GetTermination()] + if !valid { + str = "INVALID" + fmt.Println("Error", + macro.PadIdGet(), + " invalid TERM value = ", + int(dw1.GetTermination())) + } + macro.Separator().Add(str) +} + +// Generate macro to cause peripheral IRQ when configured in GPIO input mode +func ioApicRoute() bool { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + if dw0.GetGPIOInputRouteIOxAPIC() == 0 { + return false + } + + macro.Add("_APIC") + // PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) + macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") + return true +} + +// Generate macro to cause NMI when configured in GPIO input mode +func nmiRoute() bool { + macro := common.GetMacro() + if macro.Register(PAD_CFG_DW0).GetGPIOInputRouteNMI() == 0 { + return false + } + // PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT), + macro.Add("_NMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") + return true +} + +// Generate macro to cause SCI when configured in GPIO input mode +func sciRoute() bool { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + if dw0.GetGPIOInputRouteSCI() == 0 { + return false + } + // PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) + macro.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") + return true +} + +// Generate macro to cause SMI when configured in GPIO input mode +func smiRoute() bool { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + if dw0.GetGPIOInputRouteSMI() == 0 { + return false + } + // PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) + macro.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") + return true +} + +// Adds PAD_CFG_GPI macro with arguments +func (PlatformSpecific) GpiMacroAdd() { + macro := common.GetMacro() + var ids []string + macro.Set("PAD_CFG_GPI") + for routeid, isRoute := range map[string]func() (bool) { + "IOAPIC": ioApicRoute, + "SCI": sciRoute, + "SMI": smiRoute, + "NMI": nmiRoute, + } { + if isRoute() { + ids = append(ids, routeid) + } + } + + switch argc := len(ids); argc { + case 0: + // e.g. PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) + macro.Add("_TRIG_OWN").Add("(").Id().Pull().Rstsrc().Trig().Own().Add("),") + case 1: + // GPI with IRQ route + if config.AreFieldsIgnored() { + // Set Host Software Ownership to ACPI mode + macro.SetPadOwnership(common.PAD_OWN_ACPI) + } + + case 2: + // PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) + macro.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert() + macro.Add(", " + ids[0] + ", " + ids[1] + "),") + if config.AreFieldsIgnored() { + // Set Host Software Ownership to ACPI mode + macro.SetPadOwnership(common.PAD_OWN_ACPI) + } + default: + // Clear the control mask so that the check fails and "Advanced" macro is + // generated + macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields) + } +} + +// Adds PAD_CFG_GPO macro with arguments +func (platform PlatformSpecific) GpoMacroAdd() { + platform.InheritanceMacro.GpoMacroAdd() +} + +// Adds PAD_CFG_NF macro with arguments +func (platform PlatformSpecific) NativeFunctionMacroAdd() { + platform.InheritanceMacro.NativeFunctionMacroAdd() +} + +// Adds PAD_NC macro +func (platform PlatformSpecific) NoConnMacroAdd() { + platform.InheritanceMacro.NoConnMacroAdd() +} + +// GenMacro - generate pad macro +// dw0 : DW0 config register value +// dw1 : DW1 config register value +// return: string of macro +// error +func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string { + macro := common.GetInstanceMacro(PlatformSpecific{InheritanceMacro : snr.PlatformSpecific{}}, + fields.InterfaceGet()) + macro.Clear() + macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields) + macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields) + macro.PadIdSet(id).SetPadOwnership(ownership) + macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS) + macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS) + return macro.Generate() +} diff --git a/util/intelp2m/platforms/adl_h/template.go b/util/intelp2m/platforms/adl_h/template.go new file mode 100644 index 0000000..2d14448 --- /dev/null +++ b/util/intelp2m/platforms/adl_h/template.go @@ -0,0 +1,25 @@ +package adl_h + +import "../common" + +type InheritanceTemplate interface { + KeywordCheck(line string) bool +} + +// GroupNameExtract - This function extracts the group ID, if it exists in a row +// line : string from the configuration file +// return +// bool : true if the string contains a group identifier +// string : group identifier +func (PlatformSpecific) GroupNameExtract(line string) (bool, string) { + return common.KeywordsCheck(line, + "GPP_B", "GPP_T", "GPP_A", "GPP_S", "GPP_I", "GPP_H", "GPP_D", + "GPD", "GPP_C", "GPP_F", "GPP_E", "GPP_R") +} + +// KeywordCheck - This function is used to filter parsed lines of the configuration file and +// returns true if the keyword is contained in the line. +// line : string from the configuration file +func (platform PlatformSpecific) KeywordCheck(line string) bool { + return platform.InheritanceTemplate.KeywordCheck(line) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5871394bcb0636c2c803607ffb129441aa934417 Gerrit-Change-Number: 63403 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add support to control coreboot and Intel SoC features
by Maulik V Vaghela (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Nico Huber, Subrata Banik, Sridhar Siricilla, Arthur Heymans, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 17 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 10:19:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add RFC how to handle UEFI variables
by build bot (Jenkins) (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62015 ) Change subject: Documentation: Add RFC how to handle UEFI variables ...................................................................... Patch Set 6: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddf43a9ff6bf25232fbe2aa8aae2e466e5514492 Gerrit-Change-Number: 62015 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 10:10:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: option: Allow to use the EFI variable driver as option backend
by build bot (Jenkins) (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Sean Rhodes, Michał Żygowski, Patrick Rudolph, Matt DeVillier. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62562 ) Change subject: option: Allow to use the EFI variable driver as option backend ...................................................................... Patch Set 2: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I520eca96bcd573f825ed35a29bf8f750e313a02d Gerrit-Change-Number: 62562 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 10:09:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]nb/intel/sandybridge: Use a chipset devicetree
by Paul Menzel (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Arthur Heymans, Angel Pons, Alexander Couzens, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56912 ) Change subject: [WIP]nb/intel/sandybridge: Use a chipset devicetree ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Very nice. -- To view, visit https://review.coreboot.org/c/coreboot/+/56912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Gerrit-Change-Number: 56912 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 10:03:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]static.c: No linked list in early stages
by Paul Menzel (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Arthur Heymans, Martin Roth, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56913 ) Change subject: [WIP]static.c: No linked list in early stages ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56913/comment/e2121a6c_e08d0081 PS1, Line 11: On the X220 this reduces the bootblock size by 4.5K Compressed or uncompressed? https://review.coreboot.org/c/coreboot/+/56913/comment/8d88abb1_39e449e7 PS1, Line 12: Would some compiler feature like LTO help, instead of having to adapt the code? -- To view, visit https://review.coreboot.org/c/coreboot/+/56913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d32ffa19aaa587008de404ea28b8342918d817f Gerrit-Change-Number: 56913 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 10:02:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/efi: Add EFI variable store option support
by build bot (Jenkins) (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Sean Rhodes, Martin Roth, Jakub Czapiga, Matt DeVillier, Angel Pons, Arthur Heymans, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52564 ) Change subject: drivers/efi: Add EFI variable store option support ...................................................................... Patch Set 11: (1 comment) File src/drivers/efi/efivars.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145508): https://review.coreboot.org/c/coreboot/+/52564/comment/39fd31d4_d511ad93 PS11, Line 386: var_size = ALIGN_UP(header_size + hdr.NameSize + hdr.DataSize, HEADER_ALIGNMENT); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/52564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8079f71d29da5dc2db956fc68bef1486fe3906bb Gerrit-Change-Number: 52564 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 09:57:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2022