coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: drivers/smmstore: Expose region device
by Patrick Rudolph (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62014 to look at the new patch set (#4). Change subject: drivers/smmstore: Expose region device ...................................................................... drivers/smmstore: Expose region device Allow other drivers to use the SMMSTORE region device. Change-Id: I6316b703829590bd6f41c3d4013b4a4660b9cbab Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/smmstore/Makefile.inc M src/drivers/smmstore/store.c M src/include/smmstore.h 3 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/62014/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6316b703829590bd6f41c3d4013b4a4660b9cbab Gerrit-Change-Number: 62014 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: bsd/cb_err: Add error code for UEFI variable store
by Patrick Rudolph (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Patrick Rudolph, Julius Werner. Hello build bot (Jenkins), Angel Pons, Joey Madafferi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61960 to look at the new patch set (#3). Change subject: bsd/cb_err: Add error code for UEFI variable store ...................................................................... bsd/cb_err: Add error code for UEFI variable store Add a new set of errors that will be used by the introduced EFI non-volatile variable store in flash. Change-Id: I6baea9fb138d1a2755d22a3d587105793adb9c90 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/commonlib/bsd/include/commonlib/bsd/cb_err.h 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/61960/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6baea9fb138d1a2755d22a3d587105793adb9c90 Gerrit-Change-Number: 61960 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Joey Madafferi <joeymadafferi(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: [WIP]soc/intel/cannonlake: Don't use __SIMPLE_DEVICE__
by Arthur Heymans (Code Review) 06 Apr '22

06 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63399 ) Change subject: [WIP]soc/intel/cannonlake: Don't use __SIMPLE_DEVICE__ ...................................................................... [WIP]soc/intel/cannonlake: Don't use __SIMPLE_DEVICE__ Change-Id: I3c4096783695440911c09c59d8f9ca825136bf1b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/device/pnp_type.h M src/include/rules.h M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/smbus/smbus_early.c M src/superio/aspeed/common/early_config.c 9 files changed, 53 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/63399/1 diff --git a/src/include/device/pnp_type.h b/src/include/device/pnp_type.h index f0d36bd..cffc28d 100644 --- a/src/include/device/pnp_type.h +++ b/src/include/device/pnp_type.h @@ -9,7 +9,7 @@ #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) -#if defined(__SIMPLE_DEVICE__) +#if !ENV_RAMSTAGE #define ENV_PNP_SIMPLE_DEVICE 1 #else #define ENV_PNP_SIMPLE_DEVICE 0 diff --git a/src/include/rules.h b/src/include/rules.h index a7642ec..6c79196 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -321,7 +321,7 @@ * be built with simple device model. */ -#if !ENV_RAMSTAGE && !CONFIG(NO_EARLY_SIMPLE_DEVICE) +#if !ENV_RAMSTAGE && (!CONFIG(NO_EARLY_SIMPLE_DEVICE) || ENV_SMM || defined(__ACPI__)) #define __SIMPLE_DEVICE__ #endif diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 0a61381..9c5dcb2 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -114,6 +114,7 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select NO_EARLY_SIMPLE_DEVICE config MAX_CPUS int diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 578cbbf..3f9ef2b 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include "device/device.h" #include <arch/cpu.h> #include <device/pci_ops.h> #include <console/console.h> @@ -156,12 +157,12 @@ }; -static uint8_t get_dev_revision(pci_devfn_t dev) +static uint8_t get_dev_revision(const struct device *dev) { return pci_read_config8(dev, PCI_REVISION_ID); } -static uint16_t get_dev_id(pci_devfn_t dev) +static uint16_t get_dev_id(const struct device *dev) { return pci_read_config16(dev, PCI_DEVICE_ID); } @@ -201,7 +202,7 @@ static void report_mch_info(void) { int i; - pci_devfn_t dev = SA_DEV_ROOT; + const struct device *dev = SA_DEV_ROOT; uint16_t mchid = get_dev_id(dev); uint8_t mch_revision = get_dev_revision(dev); const char *mch_type = "Unknown"; @@ -220,7 +221,7 @@ static void report_pch_info(void) { int i; - pci_devfn_t dev = PCH_DEV_LPC; + const struct device *dev = PCH_DEV_LPC; uint16_t lpcid = get_dev_id(dev); const char *pch_type = "Unknown"; @@ -237,7 +238,7 @@ static void report_igd_info(void) { int i; - pci_devfn_t dev = SA_DEV_IGD; + const struct device *dev = SA_DEV_IGD; uint16_t igdid = get_dev_id(dev); const char *igd_type = "Unknown"; diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 6998eb1..0f1bded 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -20,19 +20,32 @@ #define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) #if defined(__SIMPLE_DEVICE__) #define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#else +#define SA_DEV_ROOT __pci_0_00_0 #endif #define SA_DEV_SLOT_PEG 0x01 #define SA_DEVFN_PEG0 PCI_DEVFN(SA_DEV_SLOT_PEG, 0) #define SA_DEVFN_PEG1 PCI_DEVFN(SA_DEV_SLOT_PEG, 1) -#define SA_DEVFN_PEG2 PCI_DEVFN(SA_DEV_SLOT_PEG, 2) +#define SA_DEVFN_PEG2 PCI_DEVFN(SA_DEV_SLOT_PEG, 2) +#if defined(__SIMPLE_DEVICE__) #define SA_DEV_PEG0 PCI_DEV(0, SA_DEV_SLOT_PEG, 0) #define SA_DEV_PEG1 PCI_DEV(0, SA_DEV_SLOT_PEG, 1) -#define SA_DEV_PEG2 PCI_DEV(0, SA_DEV_SLOT_PEG, 2) +#define SA_DEV_PEG2 PCI_DEV(0, SA_DEV_SLOT_PEG, 2) +#else +#define SA_DEV_PEG0 __pci_0_01_0 +#define SA_DEV_PEG1 __pci_0_01_1 +#define SA_DEV_PEG2 __pci_0_01_2 + +#endif #define SA_DEV_SLOT_IGD 0x02 -#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) -#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) +#else +#define SA_DEV_IGD __pci_0_02_0 +#endif #define SA_DEV_SLOT_TS 0x04 #define SA_DEVFN_TS PCI_DEVFN(SA_DEV_SLOT_TS, 0) @@ -202,6 +215,6 @@ #define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) #define PCH_DEV_GBE _PCH_DEV(LPC, 6) -#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7) +#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7) #endif diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 395a14d..5bb9014 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -132,6 +132,22 @@ PCI_COMMAND_MASTER); } +#else + +static uintptr_t gspi_get_base_addr(int devfn, const struct device *dev) +{ + return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); +} + +static void gspi_set_base_addr(int devfn, const struct device *dev, uintptr_t base) +{ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); + pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); +} + +#endif + void gspi_early_bar_init(void) { unsigned int gspi_bus; @@ -142,15 +158,13 @@ assert(gspi_max != 0); if (!cfg) { - printk(BIOS_ERR, "%s: No GSPI config provided by SoC!\n", - __func__); + printk(BIOS_ERR, "%s: No GSPI config provided by SoC!\n", __func__); return; } gspi_base_addr = gspi_get_early_base(); if (!gspi_base_addr) { - printk(BIOS_ERR, "%s: GSPI base address provided is NULL!\n", - __func__); + printk(BIOS_ERR, "%s: GSPI base address provided is NULL!\n", __func__); return; } @@ -158,26 +172,10 @@ if (!cfg[gspi_bus].early_init) continue; devfn = gspi_soc_bus_to_devfn(gspi_bus); - gspi_set_base_addr(devfn, NULL, - GSPI_BUS_BASE(gspi_base_addr, gspi_bus)); + gspi_set_base_addr(devfn, NULL, GSPI_BUS_BASE(gspi_base_addr, gspi_bus)); } } -#else - -static uintptr_t gspi_get_base_addr(int devfn, struct device *dev) -{ - return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); -} - -static void gspi_set_base_addr(int devfn, struct device *dev, uintptr_t base) -{ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); -} - -#endif static int gspi_read_bus_range(unsigned int *start, unsigned int *end) { diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index c359417..91b5bd1 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -38,7 +38,7 @@ static int lpss_i2c_early_init_bus(unsigned int bus) { const struct dw_i2c_bus_config *config; - pci_devfn_t dev; + const struct device *dev; int devfn; uintptr_t base; @@ -50,7 +50,7 @@ } /* Look up the controller device in the devicetree */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + dev = pcidev_path_on_root(devfn); /* Skip if not enabled for early init */ config = dw_i2c_get_soc_cfg(bus); @@ -69,7 +69,7 @@ lpss_reset_release(base); /* Ensure controller is in D0 state */ - lpss_set_power_state(dev, STATE_D0); + lpss_set_power_state(dev->path.pci.devfn, STATE_D0); /* Initialize the controller */ if (dw_i2c_init(bus, config) != CB_SUCCESS) { @@ -83,7 +83,7 @@ uintptr_t dw_i2c_base_address(unsigned int bus) { int devfn; - pci_devfn_t dev; + const struct device *dev; uintptr_t base; /* Find device+function for this controller */ @@ -92,7 +92,7 @@ return (uintptr_t)NULL; /* Form a PCI address for this device */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + dev = pcidev_path_on_root(devfn); /* Read the first base address for this device */ base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); diff --git a/src/soc/intel/common/block/smbus/smbus_early.c b/src/soc/intel/common/block/smbus/smbus_early.c index a3173f3..bddb626 100644 --- a/src/soc/intel/common/block/smbus/smbus_early.c +++ b/src/soc/intel/common/block/smbus/smbus_early.c @@ -10,7 +10,7 @@ void smbus_common_init(void) { - const pci_devfn_t dev = PCH_DEV_SMBUS; + const struct device *dev = PCH_DEV_SMBUS; /* Set SMBus I/O base address */ pci_write_config32(dev, PCI_BASE_ADDRESS_4, SMBUS_IO_BASE); diff --git a/src/superio/aspeed/common/early_config.c b/src/superio/aspeed/common/early_config.c index 716a896..79bdd11 100644 --- a/src/superio/aspeed/common/early_config.c +++ b/src/superio/aspeed/common/early_config.c @@ -11,6 +11,7 @@ uint32_t data = 0; uint8_t tmp; pnp_devfn_t dev = PNP_DEV(port, LDN_ILPC2AHB); + //const struct device *dev = dev_find_slot_pnp(port, LDN_ILPC2AHB); pnp_enter_conf_state(dev); pnp_set_logical_device(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/63399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c4096783695440911c09c59d8f9ca825136bf1b Gerrit-Change-Number: 63399 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [RFC] CBMEM: Have INIT_HOOKS in every stage
by Kyösti Mälkki (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Hung-Te Lin, Jason Glenesk, Raul Rangel, Marshall Dawson, Tim Wawrzynczak, Christian Walter, Julius Werner, Arthur Heymans, Andrey Petrov, Fred Reitberger, Yu-Ping Wu, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63375 ) Change subject: [RFC] CBMEM: Have INIT_HOOKS in every stage ...................................................................... Patch Set 2: (9 comments) Patchset: PS1: > Not a fan of the extra binary size impact that comes from this. […] I did not see an easy way to achieve the conditional parameter with preprocessor. Reviewing the changes, I am not sure we even need that. File src/arch/x86/acpi_bert_storage.c: https://review.coreboot.org/c/coreboot/+/63375/comment/8d8a20f7_eab5d26b PS2, Line 602: CBMEM_INIT_HOOK(bert_storage_setup); This does not have the characteristics of other CBMEM_INIT_HOOKS where something either migrates from CAR to CBMEM or from CBMEM to .bss. IMHO this can be delayed to any bootstate prior to OS_RESUME_CHECK. File src/lib/cbfs.c: https://review.coreboot.org/c/coreboot/+/63375/comment/fc395d4d_c131bd59 PS2, Line 698: CBMEM_CREATION_HOOK(cbfs_mcache_migrate); This file will one hook anyways for switch_to_postram_cache(), so we could combine the two and avoid adding a no-op hook. File src/lib/cbmem_console.c: https://review.coreboot.org/c/coreboot/+/63375/comment/332f324a_202c6175 PS2, Line 170: /* Run the romstage hook early so that the console region is one of the earliest created, and s/romstage/creation File src/security/tpm/tspi/log.c: https://review.coreboot.org/c/coreboot/+/63375/comment/f0b4b9c0_adba26a6 PS2, Line 157: CBMEM_CREATION_HOOK(recover_tcpa_log); We might need some more complex logic here. File src/soc/amd/stoneyridge/romstage.c: https://review.coreboot.org/c/coreboot/+/63375/comment/41fd9c1a_04cd40b6 PS1, Line 218: CBMEM_INIT_HOOK(migrate_power_state) > This looks like a functional change? Intentional? Maybe still put it in a separate commit in that ca […] Well the file was not built for postcar or ramstage, so lack of !ENV_ROMSTAGE would not have mattered. Marking resolved, the conditional will be reflected either as a parameter or different macro name. File src/soc/intel/baytrail/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/63375/comment/0ee42064_8de9c13a PS1, Line 35: CBMEM_INIT_HOOK(migrate_power_state) > Same? This doesn't look like something you'd want to run more than once? Done File src/soc/intel/braswell/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/63375/comment/12ae90e6_674f6013 PS1, Line 29: CBMEM_INIT_HOOK(migrate_power_state); > Same. Done File src/soc/intel/quark/storage_test.c: https://review.coreboot.org/c/coreboot/+/63375/comment/ae2a6f9c_14fe0fc5 PS2, Line 228: #if ENV_ROMSTAGE spurious -- To view, visit https://review.coreboot.org/c/coreboot/+/63375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Gerrit-Change-Number: 63375 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 06 Apr 2022 08:58:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/usb/pci_ehci.c: Move away from __SIMPLE_DEVICE__
by build bot (Jenkins) (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Marshall Dawson, Kyösti Mälkki, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63387 ) Change subject: drivers/usb/pci_ehci.c: Move away from __SIMPLE_DEVICE__ ...................................................................... Patch Set 3: (4 comments) File src/drivers/usb/pci_ehci.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145486): https://review.coreboot.org/c/coreboot/+/63387/comment/471a1179_6a3b7cc2 PS3, Line 91: const struct device *dbg_dev = pci_ehci_dbg_dev(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145486): https://review.coreboot.org/c/coreboot/+/63387/comment/f48e76b8_6910f620 PS3, Line 91: const struct device *dbg_dev = pci_ehci_dbg_dev(); please, no spaces at the start of a line File src/southbridge/intel/common/usb_debug.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145486): https://review.coreboot.org/c/coreboot/+/63387/comment/bd55122c_db59186b PS3, Line 13: const struct device *dev; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145486): https://review.coreboot.org/c/coreboot/+/63387/comment/805edae0_a682aed4 PS3, Line 13: const struct device *dev; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/63387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea0598e01d8fc25b08fa8f22d0622ecc729e8160 Gerrit-Change-Number: 63387 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 06 Apr 2022 08:47:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/intel/gm45: Don't use __SIMPLE_DEVICE__
by build bot (Jenkins) (Code Review) 06 Apr '22

06 Apr '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63393 ) Change subject: nb/intel/gm45: Don't use __SIMPLE_DEVICE__ ...................................................................... Patch Set 1: (9 comments) File src/northbridge/intel/gm45/igd.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145485): https://review.coreboot.org/c/coreboot/+/63393/comment/68687a38_4eea0f02 PS1, Line 18: const struct device * mch_dev = __pci_0_00_0; "foo * bar" should be "foo *bar" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145485): https://review.coreboot.org/c/coreboot/+/63393/comment/65f3bad7_b58f684a PS1, Line 19: const struct device * peg_dev = __pci_0_01_0; "foo * bar" should be "foo *bar" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145485): https://review.coreboot.org/c/coreboot/+/63393/comment/9f3e97d2_3258e5a7 PS1, Line 20: const struct device * igd_dev = __pci_0_02_0; "foo * bar" should be "foo *bar" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145485): https://review.coreboot.org/c/coreboot/+/63393/comment/3dcd7b6d_51bcb0bb PS1, Line 80: const struct device * mch_dev = PCI_DEV(0, 0, 0); "foo * bar" should be "foo *bar" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145485): https://review.coreboot.org/c/coreboot/+/63393/comment/84151de9_6aa86df3 PS1, Line 101: const struct device * mch_dev = PCI_DEV(0, 0, 0); "foo * bar" should be "foo *bar" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145485): https://review.coreboot.org/c/coreboot/+/63393/comment/0a77e07a_574d99b4 PS1, Line 112: const struct device * mch_dev = PCI_DEV(0, 0, 0); "foo * bar" should be "foo *bar" File src/northbridge/intel/gm45/iommu.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145485): https://review.coreboot.org/c/coreboot/+/63393/comment/6db5380a_2fa35f07 PS1, Line 36: const struct device * igd = __pci_0_02_0; "foo * bar" should be "foo *bar" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145485): https://review.coreboot.org/c/coreboot/+/63393/comment/11457a21_2e62c637 PS1, Line 52: const struct device * peg = __pci_0_01_0; "foo * bar" should be "foo *bar" File src/northbridge/intel/gm45/pcie.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145485): https://review.coreboot.org/c/coreboot/+/63393/comment/8c9fc3f2_9f1a4979 PS1, Line 274: const struct device * mch = __pci_0_00_0; "foo * bar" should be "foo *bar" -- To view, visit https://review.coreboot.org/c/coreboot/+/63393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27445f39d9ce9c995606229903a10d8c81c0ddb2 Gerrit-Change-Number: 63393 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 08:47:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake:[WIP] enable FSP-M compression
by Rizwan Qureshi (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Tim Wawrzynczak. Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63398 ) Change subject: soc/intel/alderlake:[WIP] enable FSP-M compression ...................................................................... soc/intel/alderlake:[WIP] enable FSP-M compression FSP-M should be compressed to reduce its footprint in SPI NOR. SinceLLC size in ADL systems in minimum of 6MB, the FSP-M can be decompressed and executed from CAR. The patch contains following changes * Enable FSP-M compression at build time * Remove FSP_M_XIP as it will be executed from CAR instead of SPI * Load and Rebase FSP-M to a newer safe address within CAR Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.corp-partner.google.com> Change-Id: Ie16e97b9445f2fe44b403bc03de55fbfb4de4da9 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/63398/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 21b1767..7420fca 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -39,8 +39,8 @@ select DISPLAY_FSP_VERSION_INFO select DRIVERS_USB_ACPI select FSP_COMPRESS_FSP_S_LZ4 + select FSP_COMPRESS_FSP_M_LZ4 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW - select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select FSP_USES_CB_DEBUG_EVENT_HANDLER select FSPS_HAS_ARCH_UPD @@ -142,6 +142,10 @@ The size of the cache-as-ram region required during bootblock and/or romstage. +config FSP_M_ADDR + hex + default 0xfa100000 + config DCACHE_BSP_STACK_SIZE hex default 0xC0000 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 095d210..82bf59c 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -60,6 +60,8 @@ CPPFLAGS_common += -I$(src)/soc/intel/alderlake CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include +$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) + ifeq ($(CONFIG_STITCH_ME_BIN),y) $(eval $(call cse_add_dummy_to_bp1_bp2,DLMP)) -- To view, visit https://review.coreboot.org/c/coreboot/+/63398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie16e97b9445f2fe44b403bc03de55fbfb4de4da9 Gerrit-Change-Number: 63398 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/*:[WIP] enable FSP-M decompression at execution
by Rizwan Qureshi (Code Review) 06 Apr '22

06 Apr '22

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63397 ) Change subject: soc/intel/*:[WIP] enable FSP-M decompression at execution ...................................................................... soc/intel/*:[WIP] enable FSP-M decompression at execution FSP-M is compressed and is not more XIP. Hence remove the FSP_M_XIP config. The FSP-M decompression requires more CAR memory. Increase CAR region size to 2.5 MB. As per the system adress MAP we will be breaching the LAPIC base address and HPET addresses hence rebase the CAR memory to somewhere safe. Also increase the required stack szie Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.corp-partner.google.com> Change-Id: If2a20b0e81a116a81170363f7b93c845cde863f8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S 2 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/63397/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 25d11d3..21b1767 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -134,17 +134,17 @@ default 24 config DCACHE_RAM_BASE - default 0xfef00000 + default 0xfa000000 config DCACHE_RAM_SIZE - default 0xc0000 + default 0x280000 help The size of the cache-as-ram region required during bootblock and/or romstage. config DCACHE_BSP_STACK_SIZE hex - default 0x80400 + default 0xC0000 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 1c905a4..c6f7f74 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -178,7 +178,7 @@ or $MTRR_PHYS_MASK_VALID, %eax movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ wrmsr -#elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */ +#elif (CONFIG_DCACHE_RAM_SIZE == 2560 * KiB) /* 2560 KiB */ find_free_mtrr test %ebx, %ebx jz .halt_forever @@ -190,7 +190,7 @@ wrmsr incl %ecx - mov $(512 * KiB), %eax /* size mask */ + mov $(2048 * KiB), %eax /* size mask */ dec %eax not %eax or $MTRR_PHYS_MASK_VALID, %eax @@ -201,13 +201,13 @@ test %ebx, %ebx jz .halt_forever 1: - mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax + mov $(CONFIG_DCACHE_RAM_BASE + 2048 * KiB), %eax or $MTRR_TYPE_WRBACK, %eax xor %edx,%edx wrmsr incl %ecx - mov $(256 * KiB), %eax /* size mask */ + mov $(512 * KiB), %eax /* size mask */ dec %eax not %eax or $MTRR_PHYS_MASK_VALID, %eax -- To view, visit https://review.coreboot.org/c/coreboot/+/63397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2a20b0e81a116a81170363f7b93c845cde863f8 Gerrit-Change-Number: 63397 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: Documentation: Add dasharo to after-market firmware list
by Igor Bagnucki (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Igor Bagnucki. Hello Igor Bagnucki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63396 to review the following change. Change subject: Documentation: Add dasharo to after-market firmware list ...................................................................... Documentation: Add dasharo to after-market firmware list Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Change-Id: I19dbf70bc9ceec1408944c4029db6eabd5e2254d --- M Documentation/distributions.md 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/63396/1 diff --git a/Documentation/distributions.md b/Documentation/distributions.md index 4d69fcc..5706b49 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -54,6 +54,15 @@ built entirely from source code. Their copy of the coreboot repository is therefore stripped of all devices that require binary components to boot. + +### Dasharo + +[Dasharo](https://dasharo.com/) is open source firmware distribution focusing on +clean and simple code, long-term maintenance, transparent validation, +privacy-respecting implementation, liberty for the owners, and trustworthiness +for all. + + ### MrChromebox [MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware -- To view, visit https://review.coreboot.org/c/coreboot/+/63396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19dbf70bc9ceec1408944c4029db6eabd5e2254d Gerrit-Change-Number: 63396 Gerrit-PatchSet: 1 Gerrit-Owner: Igor Bagnucki Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [WIP] FMAP: Refactor CBMEM hook
by Kyösti Mälkki (Code Review) 06 Apr '22

06 Apr '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63395 ) Change subject: [WIP] FMAP: Refactor CBMEM hook ...................................................................... [WIP] FMAP: Refactor CBMEM hook Change-Id: Ib1257c57c64322c8c3dccdf1a754afb9b54ce7f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/lib/fmap.c 1 file changed, 11 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/63395/1 diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 2511255..4d197db 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -273,7 +273,7 @@ return rdev_writeat(&rdev, buffer, 0, size); } -static void fmap_register_cbmem_cache(int unused) +static void fmap_register_cbmem_cache(void) { const struct cbmem_entry *e; @@ -290,7 +290,7 @@ * The main reason to copy the FMAP into CBMEM is to make it available to the * OS on every architecture. As side effect use the CBMEM copy as cache. */ -static void fmap_setup_cbmem_cache(int unused) +static void fmap_add_cbmem_cache(void) { struct region_device fmrd; @@ -311,11 +311,17 @@ cbmem_entry_remove(cbmem_entry_find(CBMEM_ID_FMAP)); return; } +} + +static void fmap_setup_cbmem_cache(int unused) +{ + if (ENV_ROMSTAGE) + fmap_add_cbmem_cache(); /* Finally advertise the cache for the current stage */ - fmap_register_cbmem_cache(unused); + fmap_register_cbmem_cache(); } ROMSTAGE_CBMEM_INIT_HOOK(fmap_setup_cbmem_cache) -RAMSTAGE_CBMEM_INIT_HOOK(fmap_register_cbmem_cache) -POSTCAR_CBMEM_INIT_HOOK(fmap_register_cbmem_cache) +RAMSTAGE_CBMEM_INIT_HOOK(fmap_setup_cbmem_cache) +POSTCAR_CBMEM_INIT_HOOK(fmap_setup_cbmem_cache) -- To view, visit https://review.coreboot.org/c/coreboot/+/63395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1257c57c64322c8c3dccdf1a754afb9b54ce7f8 Gerrit-Change-Number: 63395 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022