coreboot-gerrit April 2022

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Change in coreboot[master]: [RFC] CBMEM: Have INIT_HOOKS in every stage
by Kyösti Mälkki (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Hung-Te Lin, Jason Glenesk, Raul Rangel, Marshall Dawson, Tim Wawrzynczak, Christian Walter, Arthur Heymans, Kyösti Mälkki, Andrey Petrov, Fred Reitberger, Yu-Ping Wu, Felix Held. Hello Hung-Te Lin, build bot (Jenkins), Raul Rangel, Julius Werner, Arthur Heymans, Andrey Petrov, Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Christian Walter, Fred Reitberger, Yu-Ping Wu, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63375 to look at the new patch set (#2). Change subject: [RFC] CBMEM: Have INIT_HOOKS in every stage ...................................................................... [RFC] CBMEM: Have INIT_HOOKS in every stage There are efforts to have bootflows that do not follow a traditional bootblock-romstage-postcar-ramstage model. As part of that CBMEM initialisation hooks will need to move from romstage to bootblock. Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/acpi_bert_storage.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/usb/ehci_debug.c M src/drivers/vpd/vpd.c M src/include/cbmem.h M src/include/rules.h M src/lib/cbfs.c M src/lib/cbmem_console.c M src/lib/ext_stage_cache.c M src/lib/fmap.c M src/lib/timestamp.c M src/security/tpm/tspi/log.c M src/security/vboot/common.c M src/soc/amd/common/block/pm/chipset_state.c M src/soc/amd/common/pi/heapmanager.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/quark/storage_test.c M src/soc/mediatek/common/memory.c M src/soc/qualcomm/common/qclib.c 23 files changed, 54 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/63375/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Gerrit-Change-Number: 63375 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/inteltool: Add support for Alder Lake chips detection and GPIOs
by Michał Kopeć (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Michał Żygowski, Stefan Reinauer. Hello build bot (Jenkins), Michał Żygowski, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63374 to look at the new patch set (#7). Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs ...................................................................... util/inteltool: Add support for Alder Lake chips detection and GPIOs Add PCI IDs for Alder Lake H devices and their GPIO tables. TEST: dump GPIOs on i5-12600K with Z690 chipset Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/alderlake_h.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 616 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63374/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6 Gerrit-Change-Number: 63374 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/inteltool: Add support for Alder Lake chips detection and GPIOs
by Michał Kopeć (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Michał Żygowski, Stefan Reinauer. Hello build bot (Jenkins), Michał Żygowski, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63374 to look at the new patch set (#6). Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs ...................................................................... util/inteltool: Add support for Alder Lake chips detection and GPIOs Add PCI IDs for Alder Lake H devices and their GPIO tables. TEST: dump GPIOs on i5-12600K with Z690 chipset Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/alderlake_h.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 616 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63374/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6 Gerrit-Change-Number: 63374 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/usb/pci_ehci.c: Move away from __SIMPLE_DEVICE__
by Arthur Heymans (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Marshall Dawson, Kyösti Mälkki, Felix Held. Hello Marshall Dawson, Kyösti Mälkki, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63387 to look at the new patch set (#4). Change subject: drivers/usb/pci_ehci.c: Move away from __SIMPLE_DEVICE__ ...................................................................... drivers/usb/pci_ehci.c: Move away from __SIMPLE_DEVICE__ Change-Id: Iea0598e01d8fc25b08fa8f22d0622ecc729e8160 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/pci_device.c M src/drivers/usb/pci_ehci.c M src/include/device/pci.h M src/include/device/pci_ehci.h M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/intel/broadwell/pch/usb_debug.c M src/southbridge/amd/agesa/hudson/enable_usbdebug.c M src/southbridge/amd/pi/hudson/enable_usbdebug.c M src/southbridge/intel/common/usb_debug.c 9 files changed, 54 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/63387/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea0598e01d8fc25b08fa8f22d0622ecc729e8160 Gerrit-Change-Number: 63387 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: allow MKBP devices and disable TBMC device
by Kenneth Chan (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Rob Barnes, Karthik Ramasubramanian. Kenneth Chan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63394 ) Change subject: mb/google/guybrush: allow MKBP devices and disable TBMC device ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9980f2b5bf10b12f2bd666212b5bce925dc323d Gerrit-Change-Number: 63394 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 08:16:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: allow MKBP devices and disable TBMC device
by Kenneth Chan (Code Review) 06 Apr '22

06 Apr '22

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63394 ) Change subject: mb/google/guybrush: allow MKBP devices and disable TBMC device ...................................................................... mb/google/guybrush: allow MKBP devices and disable TBMC device Enable MKBP (Matrix Keyboard Protocol) interface for all guybrush family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:227240985 BRANCH=guybrush TEST=manual test on Dewatt: Volume Up/Down and Power buttons, Tablet Mode switch Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: Ic9980f2b5bf10b12f2bd666212b5bce925dc323d --- M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/63394/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h index 2ce5fd5..5695a8e 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h @@ -54,13 +54,13 @@ /* Set GPI for SCI */ #define EC_SCI_GPI GEVENT_24 /* eSPI system event -> GPE 24 */ +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GEVENT_3 /* AGPIO 22 -> GPE 3 */ -/* Enable Tablet switch */ -#define EC_ENABLE_TBMC_DEVICE - #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9980f2b5bf10b12f2bd666212b5bce925dc323d Gerrit-Change-Number: 63394 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/usb/pci_ehci.c: Move away from __SIMPLE_DEVICE__
by Arthur Heymans (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Marshall Dawson, Kyösti Mälkki, Felix Held. Hello Marshall Dawson, Kyösti Mälkki, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63387 to look at the new patch set (#3). Change subject: drivers/usb/pci_ehci.c: Move away from __SIMPLE_DEVICE__ ...................................................................... drivers/usb/pci_ehci.c: Move away from __SIMPLE_DEVICE__ Change-Id: Iea0598e01d8fc25b08fa8f22d0622ecc729e8160 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/pci_device.c M src/drivers/usb/pci_ehci.c M src/include/device/pci.h M src/include/device/pci_ehci.h M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/intel/broadwell/pch/usb_debug.c M src/southbridge/amd/agesa/hudson/enable_usbdebug.c M src/southbridge/amd/pi/hudson/enable_usbdebug.c M src/southbridge/intel/common/usb_debug.c 9 files changed, 57 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/63387/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea0598e01d8fc25b08fa8f22d0622ecc729e8160 Gerrit-Change-Number: 63387 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/gm45: Don't use __SIMPLE_DEVICE__
by Arthur Heymans (Code Review) 06 Apr '22

06 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63393 ) Change subject: nb/intel/gm45: Don't use __SIMPLE_DEVICE__ ...................................................................... nb/intel/gm45: Don't use __SIMPLE_DEVICE__ Change-Id: I27445f39d9ce9c995606229903a10d8c81c0ddb2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/early_init.c M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/romstage.c M src/southbridge/intel/i82801ix/dmi_setup.c M src/southbridge/intel/i82801ix/early_init.c 10 files changed, 46 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63393/1 diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 3f632a1..f5ea1f5 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -12,6 +12,7 @@ select INTEL_EDID select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF + select NO_EARLY_SIMPLE_DEVICE config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index e911064..ee8b0f2 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -6,7 +6,7 @@ void gm45_early_init(void) { - const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); + const struct device *d0f0 = __pci_0_00_0; /* Setup MCHBAR. */ pci_write_config32(d0f0, D0F0_MCHBAR_LO, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index d610f31..bb067d4 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -203,7 +203,7 @@ /* * Graphics frequencies */ -#define GCFGC_PCIDEV PCI_DEV(0, 2, 0) +#define GCFGC_PCIDEV __pci_0_02_0 #define GCFGC_OFFSET 0xf0 #define GCFGC_CR_SHIFT 0 #define GCFGC_CR_MASK (0xf << GCFGC_CR_SHIFT) diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 7b0b1e5..bd7e391 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -15,9 +15,9 @@ /* The PEG settings have to be set before ASPM is setup on DMI. */ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) { - const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0); - const pci_devfn_t peg_dev = PCI_DEV(0, 1, 0); - const pci_devfn_t igd_dev = PCI_DEV(0, 2, 0); + const struct device * mch_dev = __pci_0_00_0; + const struct device * peg_dev = __pci_0_01_0; + const struct device * igd_dev = __pci_0_02_0; printk(BIOS_DEBUG, "Enabling IGD.\n"); @@ -77,7 +77,7 @@ static void disable_igd(const sysinfo_t *const sysinfo) { - const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0); + const struct device * mch_dev = PCI_DEV(0, 0, 0); printk(BIOS_DEBUG, "Disabling IGD.\n"); @@ -98,7 +98,7 @@ void init_igd(const sysinfo_t *const sysinfo) { - const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0); + const struct device * mch_dev = PCI_DEV(0, 0, 0); const u8 capid = pci_read_config8(mch_dev, D0F0_CAPID0 + 4); if (!sysinfo->enable_igd || (capid & (1 << (33 - 32)))) @@ -109,7 +109,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo) { - const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0); + const struct device * mch_dev = PCI_DEV(0, 0, 0); const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4); if (!sysinfo->enable_igd || (capid & (1 << (33 - 32)))) diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 4199f8b..54f2de1 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -11,8 +11,8 @@ void init_iommu(void) { /* FIXME: proper test? */ - int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff; - int stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); + int me_active = pci_read_config8(__pci_0_03_0, PCI_CLASS_REVISION) != 0xff; + int stepping = pci_read_config8(__pci_0_00_0, PCI_CLASS_REVISION); mchbar_write32(0x28, IOMMU_BASE1 | 1); /* HDA @ 0:1b.0 */ if (stepping != STEPPING_B2) { @@ -31,9 +31,9 @@ mchbar_write32(0x20, IOMMU_BASE4 | 1); /* all other DMA sources */ /* clear GTT */ - u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC); + u16 gtt = pci_read_config16(__pci_0_00_0, D0F0_GGC); if (gtt & 0x400) { /* VT mode */ - const pci_devfn_t igd = PCI_DEV(0, 2, 0); + const struct device * igd = __pci_0_02_0; /* setup somewhere */ pci_or_config16(igd, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); @@ -49,7 +49,7 @@ if (stepping == STEPPING_B3) { mchbar_setbits8(0xffc, 1 << 4); - const pci_devfn_t peg = PCI_DEV(0, 1, 0); + const struct device * peg = __pci_0_01_0; /* FIXME: proper test? */ if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 295bf5b..c9c292f 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -93,8 +93,8 @@ const int sdvo_enabled, const int peg_x16) { - const pci_devfn_t mch = PCI_DEV(0, 0, 0); - const pci_devfn_t pciex = PCI_DEV(0, 1, 0); + const struct device *mch = __pci_0_00_0; + const struct device *pciex = __pci_0_01_0; printk(BIOS_DEBUG, "PEG x%d %s, SDVO %s\n", peg_x16?16:1, peg_enabled?"enabled":"disabled", @@ -136,7 +136,7 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled) { u32 tmp32; - const pci_devfn_t pciex = PCI_DEV(0, 1, 0); + const struct device *pciex = __pci_0_01_0; /* Prerequisites for ASPM: */ if (peg_enabled) { @@ -221,7 +221,7 @@ /* Exit latencies should be checked to be supported by the endpoint (ICH), but ICH doesn't give any limits. */ - if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) + if (LPC_IS_MOBILE(__pci_0_1f_0)) dmibar_setbits8(DMILCTL, 3 << 0); // enable ASPM L0s, L1 (write-once) else dmibar_setbits8(DMILCTL, 1 << 0); // enable ASPM L0s (write-once) @@ -271,7 +271,7 @@ void gm45_late_init(const stepping_t stepping) { - const pci_devfn_t mch = PCI_DEV(0, 0, 0); + const struct device * mch = __pci_0_00_0; const int peg_enabled = (pci_read_config8(mch, D0F0_DEVEN) >> 1) & 1; const int sdvo_enabled = mchbar_read16(0x40) >> 8 & 1; const int peg_x16 = (peg_enabled && !sdvo_enabled); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 35d71c0..e6f0e82 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -30,7 +30,7 @@ void get_gmch_info(sysinfo_t *sysinfo) { - sysinfo->stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); + sysinfo->stepping = pci_read_config8(__pci_0_00_0, PCI_CLASS_REVISION); if ((sysinfo->stepping > STEPPING_B3) && (sysinfo->stepping != STEPPING_CONVERSION_A1)) die("Unknown stepping.\n"); @@ -43,12 +43,12 @@ sysinfo->cores = ((eax >> 26) & 0x3f) + 1; printk(BIOS_SPEW, "%d CPU cores\n", sysinfo->cores); - u32 capid = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_CAPID0+8); + u32 capid = pci_read_config16(__pci_0_00_0, D0F0_CAPID0+8); if (!(capid & (1<<(79-64)))) { printk(BIOS_SPEW, "iTPM enabled\n"); } - capid = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0+4); + capid = pci_read_config32(__pci_0_00_0, D0F0_CAPID0+4); if (!(capid & (1<<(57-32)))) { printk(BIOS_SPEW, "ME enabled\n"); } @@ -142,7 +142,7 @@ printk(BIOS_SPEW, "PCIe-to-GMCH enabled\n"); } - capid = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0); + capid = pci_read_config32(__pci_0_00_0, D0F0_CAPID0); u32 ddr_cap = capid>>30 & 0x3; switch (ddr_cap) { @@ -191,7 +191,7 @@ void enter_raminit_or_reset(void) { /* Interrupted RAM init or inconsistent system? */ - u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + u8 reg8 = pci_read_config8(__pci_0_1f_0, 0xa2); if (reg8 & (1 << 2)) { /* S4-assertion-width violation */ /* Ignore S4-assertion-width violation like original BIOS. */ @@ -201,18 +201,18 @@ if (reg8 & (1 << 7)) { /* interrupted RAM init */ /* Don't enable S4-assertion stretch. Makes trouble on roda/rk9. - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8 | 0x08); + reg8 = pci_read_config8(__pci_0_1f_0, 0xa4); + pci_write_config8(__pci_0_1f_0, 0xa4, reg8 | 0x08); */ /* Clear bit7. */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~(1 << 7)); + pci_write_config8(__pci_0_1f_0, 0xa2, reg8 & ~(1 << 7)); printk(BIOS_INFO, "Interrupted RAM init, reset required.\n"); gm45_early_reset(); } /* Mark system to be in RAM init. */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 | (1 << 7)); + pci_write_config8(__pci_0_1f_0, 0xa2, reg8 | (1 << 7)); } /* For a detected DIMM, test the value of an SPD byte to @@ -1225,17 +1225,17 @@ } /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, which requires to have TSEG_BASE aligned to TSEG_SIZE. */ - pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); + pci_update_config8(__pci_0_00_0, D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); uma_sizem += 2; } const unsigned int mmio_size = get_mmio_size(); const unsigned int MMIOstart = 4096 - mmio_size + uma_sizem; - const int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff; + const int me_active = pci_read_config8(__pci_0_03_0, PCI_CLASS_REVISION) != 0xff; const unsigned int ME_SIZE = prejedec || !me_active ? 0 : 32; const unsigned int usedMEsize = (total_mb[0] != total_mb[1]) ? ME_SIZE : 2 * ME_SIZE; const unsigned int claimCapable = - !(pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0 + 4) & (1 << (47 - 32))); + !(pci_read_config32(__pci_0_00_0, D0F0_CAPID0 + 4) & (1 << (47 - 32))); const unsigned int TOM = total_mb[0] + total_mb[1]; unsigned int TOMminusME = TOM - usedMEsize; @@ -1260,11 +1260,11 @@ REMAPlimit -= 64; } - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, (TOM >> 7) & 0x1ff); - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, TOLUD << 4); - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, TOUUD); - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_REMAPBASE, (REMAPbase >> 6) & 0x03ff); - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_REMAPLIMIT, (REMAPlimit >> 6) & 0x03ff); + pci_write_config16(__pci_0_00_0, D0F0_TOM, (TOM >> 7) & 0x1ff); + pci_write_config16(__pci_0_00_0, D0F0_TOLUD, TOLUD << 4); + pci_write_config16(__pci_0_00_0, D0F0_TOUUD, TOUUD); + pci_write_config16(__pci_0_00_0, D0F0_REMAPBASE, (REMAPbase >> 6) & 0x03ff); + pci_write_config16(__pci_0_00_0, D0F0_REMAPLIMIT, (REMAPlimit >> 6) & 0x03ff); /* Program channel mode. */ switch (mode) { @@ -1553,9 +1553,9 @@ mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_CMD_NOP); - pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); + pci_and_config8(__pci_0_00_0, 0xf0, ~(1 << 2)); - pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2); + pci_or_config8(__pci_0_00_0, 0xf0, 1 << 2); udelay(2); /* 5 6 7 8 9 10 11 12 */ @@ -1765,9 +1765,9 @@ /* Announce normal operation, initialization completed. */ mchbar_setbits32(DCC_MCHBAR, 0x7 << 16 | 0x1 << 19); - pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2); + pci_or_config8(__pci_0_00_0, 0xf0, 1 << 2); - pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); + pci_and_config8(__pci_0_00_0, 0xf0, ~(1 << 2)); /* Take a breath (the reader). */ @@ -1798,7 +1798,7 @@ dram_optimizations(timings, dimms); /* Mark raminit being finished. :-) */ - pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7)); + pci_and_config8(__pci_0_1f_0, 0xa2, (u8)~(1 << 7)); raminit_thermal(sysinfo); init_igd(sysinfo); diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 744c92b..9edf83f 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -13,8 +13,8 @@ #include <southbridge/intel/common/pmutil.h> #include <string.h> -#define LPC_DEV PCI_DEV(0, 0x1f, 0) -#define MCH_DEV PCI_DEV(0, 0, 0) +#define LPC_DEV __pci_0_1f_0 +#define MCH_DEV __pci_0_00_0 void __weak mb_setup_superio(void) { diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index f8b418d..5dd483a 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -69,7 +69,7 @@ RCBA32(RCBA_ULBA) = (uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE; /* Enable ASPM. */ - if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) { + if (LPC_IS_MOBILE(__pci_0_1f_0)) { reg32 = RCBA32(RCBA_DMC); /* Enable mobile specific power saving (set this first). */ reg32 = (reg32 & ~(3 << 10)) | (1 << 10); diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index f781098..627830f 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -9,7 +9,7 @@ void i82801ix_lpc_setup(void) { - const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + const struct device *d31f0 = __pci_0_1f_0; const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_i82801ix_config *config; @@ -45,7 +45,7 @@ void i82801ix_early_init(void) { - const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + const struct device *d31f0 = __pci_0_1f_0; if (ENV_ROMSTAGE) enable_smbus(); -- To view, visit https://review.coreboot.org/c/coreboot/+/63393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27445f39d9ce9c995606229903a10d8c81c0ddb2 Gerrit-Change-Number: 63393 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common/smihandler: Explicitly define __SIMPLE_DEVICE__
by Arthur Heymans (Code Review) 06 Apr '22

06 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63392 ) Change subject: sb/intel/common/smihandler: Explicitly define __SIMPLE_DEVICE__ ...................................................................... sb/intel/common/smihandler: Explicitly define __SIMPLE_DEVICE__ Change-Id: Idb8bf9558d5328567c8f58388cd0ad4e9cfdc79c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/smihandler.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/63392/1 diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 798f2f1..b60e7d3 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#define __SIMPLE_DEVICE__ + #include <types.h> #include <arch/io.h> #include <device/pci_ops.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/63392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb8bf9558d5328567c8f58388cd0ad4e9cfdc79c Gerrit-Change-Number: 63392 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: sb/intel/common/early_{spi/smbus}: Don't use __SIMPLE_DEVICE__
by Arthur Heymans (Code Review) 06 Apr '22

06 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63391 ) Change subject: sb/intel/common/early_{spi/smbus}: Don't use __SIMPLE_DEVICE__ ...................................................................... sb/intel/common/early_{spi/smbus}: Don't use __SIMPLE_DEVICE__ Change-Id: I93094dd56c0b97c9ddf5476cb723cddf0accb303 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/early_smbus.c M src/southbridge/intel/common/early_smbus.h M src/southbridge/intel/common/early_spi.h 3 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/63391/1 diff --git a/src/southbridge/intel/common/early_smbus.c b/src/southbridge/intel/common/early_smbus.c index 6078b5f..8535857 100644 --- a/src/southbridge/intel/common/early_smbus.c +++ b/src/southbridge/intel/common/early_smbus.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#undef __SIMPLE_DEVICE__ + #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> @@ -14,7 +16,7 @@ int smbus_enable_iobar(uintptr_t base) { /* Set the SMBus device statically. */ - const pci_devfn_t dev = PCI_DEV_SMBUS; + const struct device *dev = PCI_DEV_SMBUS; /* Check to make sure we've got the right device. */ if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_INTEL) diff --git a/src/southbridge/intel/common/early_smbus.h b/src/southbridge/intel/common/early_smbus.h index d6a7cbb..bf3b4ba 100644 --- a/src/southbridge/intel/common/early_smbus.h +++ b/src/southbridge/intel/common/early_smbus.h @@ -5,7 +5,7 @@ #include <device/pci_def.h> -#define PCI_DEV_SMBUS PCI_DEV(0, 0x1f, 3) +#define PCI_DEV_SMBUS __pci_0_1f_3 #define SMB_BASE PCI_BASE_ADDRESS_4 #define HOSTC 0x40 diff --git a/src/southbridge/intel/common/early_spi.h b/src/southbridge/intel/common/early_spi.h index ae84f74..dc26f42 100644 --- a/src/southbridge/intel/common/early_spi.h +++ b/src/southbridge/intel/common/early_spi.h @@ -3,11 +3,13 @@ #ifndef SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H #define SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H +#undef __SIMPLE_DEVICE__ + #include <device/pci_ops.h> static inline void enable_spi_prefetching_and_caching(void) { - pci_update_config8(PCI_DEV(0, 0x1f, 0), 0xdc, ~(3 << 2), 2 << 2); + pci_update_config8(__pci_0_1f_0, 0xdc, ~(3 << 2), 2 << 2); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/63391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93094dd56c0b97c9ddf5476cb723cddf0accb303 Gerrit-Change-Number: 63391 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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