coreboot-gerrit April 2022

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Yu-Ping Wu (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Rex-BC Chen, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 6: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63251/comment/a495c87b_5aeb02d4 PS6, Line 9: function functions https://review.coreboot.org/c/coreboot/+/63251/comment/cbb65010_b42262a4 PS6, Line 10: through from https://review.coreboot.org/c/coreboot/+/63251/comment/ff301eab_60d7a2b3 PS6, Line 13: , add new API . Therefore, new API is added https://review.coreboot.org/c/coreboot/+/63251/comment/115f049d_0da4eb4c PS6, Line 15: libpayload payloads File payloads/libpayload/include/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/916d8991_1318535a PS6, Line 278: uint32_t config_size; Move config_size below config_base. File payloads/libpayload/include/sysinfo.h: https://review.coreboot.org/c/coreboot/+/63251/comment/185e230d_61e79604 PS4, Line 87: struct { > Done, I use memcpy to fill the structure, I'm not sure which one is better, any suggestions? Both methods should be fine. File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/8c74d129_14c0c678 PS6, Line 176: uint32_t config_size; Same. -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 6 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 07:39:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/usb/pcui_ehci.c: Move away from __SIMPLE_DEVICE__
by Arthur Heymans (Code Review) 06 Apr '22

06 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63387 ) Change subject: drivers/usb/pcui_ehci.c: Move away from __SIMPLE_DEVICE__ ...................................................................... drivers/usb/pcui_ehci.c: Move away from __SIMPLE_DEVICE__ Change-Id: Iea0598e01d8fc25b08fa8f22d0622ecc729e8160 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/pci_device.c M src/drivers/usb/pci_ehci.c M src/include/device/pci.h M src/include/device/pci_ehci.h M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/intel/broadwell/pch/usb_debug.c M src/southbridge/amd/agesa/hudson/enable_usbdebug.c M src/southbridge/amd/pi/hudson/enable_usbdebug.c M src/southbridge/intel/common/usb_debug.c 9 files changed, 57 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/63387/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 90b26c1..aa82c9e 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1284,19 +1284,6 @@ } /** - * Test for match between romstage and ramstage device instance. - * - * @param dev Pointer to the device structure. - * @param sdev Simple device model identifier, created with PCI_DEV(). - * @return Non-zero if bus:dev.fn of device matches. - */ -unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev) -{ - return dev->bus->secondary == PCI_DEV2SEGBUS(sdev) && - dev->path.pci.devfn == PCI_DEV2DEVFN(sdev); -} - -/** * PCI devices that are marked as "hidden" do not get probed. However, the same * initialization logic is still performed as if it were. This is useful when * devices would like to be described in the devicetree.cb file, and/or present diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 8e85426..2f56452 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#undef __SIMPLE_DEVICE__ + #include <console/console.h> #include <device/pci_ehci.h> #include <device/mmio.h> @@ -18,39 +20,39 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) { - pci_devfn_t dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + const struct device *dev = pci_ehci_dbg_dev(); /* We only support controllers on bus 0. */ - if (PCI_DEV2SEGBUS(dev) != 0) + if (dev->bus->secondary != 0) return -1; - u32 class = pci_s_read_config32(dev, PCI_CLASS_REVISION) >> 8; + u32 class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; if (class != PCI_EHCI_CLASSCODE) return -1; - u8 pm_cap = pci_s_find_capability(dev, PCI_CAP_ID_PM); + u8 pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM); if (pm_cap) { - u16 pm_ctrl = pci_s_read_config16(dev, pm_cap + PCI_PM_CTRL); + u16 pm_ctrl = pci_read_config16(dev, pm_cap + PCI_PM_CTRL); /* Set to D0 and disable PM events. */ pm_ctrl &= ~PCI_PM_CTRL_PME_ENABLE; pm_ctrl &= ~PCI_PM_CTRL_STATE_MASK; - pci_s_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl); + pci_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl); } - u8 pos = pci_s_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG); + u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG); if (!pos) return -1; - u32 cap = pci_s_read_config32(dev, pos); + u32 cap = pci_read_config32(dev, pos); /* FIXME: We should remove static EHCI_BAR_INDEX. */ u8 ehci_bar = 0x10 + 4 * ((cap >> 29) - 1); if (ehci_bar != EHCI_BAR_INDEX) return -1; - pci_s_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR); + pci_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR); - pci_s_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); *base = CONFIG_EHCI_BAR; @@ -61,7 +63,7 @@ void ehci_debug_select_port(unsigned int port) { - pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + const struct device *dbg_dev = pci_ehci_dbg_dev(); pci_ehci_dbg_set_port(dbg_dev, port); } @@ -86,9 +88,9 @@ void pci_ehci_read_resources(struct device *dev) { - pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + const struct device *dbg_dev = pci_ehci_dbg_dev(); - if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) { + if (!ehci_drv_ops && dbg_dev == dev) { memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops)); ehci_drv_ops = dev->ops; ehci_dbg_ops.set_resources = pci_ehci_set_resources; @@ -102,9 +104,9 @@ } #endif -u8 *pci_ehci_base_regs(pci_devfn_t sdev) +u8 *pci_ehci_base_regs(const struct device *sdev) { - u32 bar = pci_s_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f; + u32 bar = pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f; u8 *base = (u8 *)(uintptr_t)bar; return base + HC_LENGTH(read32(base)); } diff --git a/src/include/device/pci.h b/src/include/device/pci.h index db7cc69..50d9700 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -94,7 +94,6 @@ void pci_dev_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device); void pci_dev_init(struct device *dev); -unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev); const char *pin_to_str(int pin); int get_pci_irq_pins(struct device *dev, struct device **parent_bdg); diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index e7a445d..88ee2b5 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -13,10 +13,10 @@ /* Return PCI BDF for an EHCI controller by a given index. PCI function * must already be powered to respond to configuration requests. */ -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx); +const struct device *pci_ehci_dbg_dev(void); -u8 *pci_ehci_base_regs(pci_devfn_t dev); -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port); +u8 *pci_ehci_base_regs(const struct device *dev); +void pci_ehci_dbg_set_port(const struct device *dev, unsigned int port); #if !CONFIG(USBDEBUG) #define pci_ehci_read_resources pci_dev_read_resources diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index ca02a69..2beca8a 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ +#undef __SIMPLE_DEVICE__ #include <stdint.h> #include <device/pci_ops.h> @@ -11,13 +10,13 @@ #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +const struct device *pci_ehci_dbg_dev(unsigned int hcd_idx) { pm_io_write8(PM_USB_ENABLE, PM_USB_ALL_CONTROLLERS); return SOC_EHCI1_DEV; } -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +void pci_ehci_dbg_set_port(const struct device *dev, unsigned int port) { u32 reg32, value; diff --git a/src/soc/intel/broadwell/pch/usb_debug.c b/src/soc/intel/broadwell/pch/usb_debug.c index 0fda336..59a52ec 100644 --- a/src/soc/intel/broadwell/pch/usb_debug.c +++ b/src/soc/intel/broadwell/pch/usb_debug.c @@ -1,17 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ +#undef __SIMPLE_DEVICE__ #include <device/pci_ehci.h> #include <device/pci_def.h> -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +const struct device *pci_ehci_dbg_dev() { - return PCI_DEV(0, 0x1d, 0); + return __pci_0_1d_0; } -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +void pci_ehci_dbg_set_port(const struct device *dev, unsigned int port) { /* Hardcoded to physical port 1 */ } diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 9dda666..41a017a 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ +#undef __SIMPLE_DEVICE__ #include <stdint.h> #include <arch/io.h> @@ -12,21 +11,21 @@ #define DEBUGPORT_MISC_CONTROL 0x80 -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +const struct device *pci_ehci_dbg_dev(void) { /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA); - if (hcd_idx == 3) - return PCI_DEV(0, 0x16, 2); - else if (hcd_idx == 2) - return PCI_DEV(0, 0x13, 2); + if (CONFIG_USBDEBUG_HCD_INDEX == 3) + return __pci_0_16_0; + else if (CONFIG_USBDEBUG_HCD_INDEX == 2) + return __pci_0_13_0; else - return PCI_DEV(0, 0x12, 2); + return __pci_0_12_0; } -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +void pci_ehci_dbg_set_port(const struct device *dev, unsigned int port) { u8 *base_regs = pci_ehci_base_regs(dev); u32 reg32; diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c index 8462c2b..41a017a 100644 --- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ +#undef __SIMPLE_DEVICE__ #include <stdint.h> #include <arch/io.h> @@ -12,21 +11,21 @@ #define DEBUGPORT_MISC_CONTROL 0x80 -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +const struct device *pci_ehci_dbg_dev(void) { /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA); - if (hcd_idx == 3) - return PCI_DEV(0, 0x16, 0); - else if (hcd_idx == 2) - return PCI_DEV(0, 0x13, 0); + if (CONFIG_USBDEBUG_HCD_INDEX == 3) + return __pci_0_16_0; + else if (CONFIG_USBDEBUG_HCD_INDEX == 2) + return __pci_0_13_0; else - return PCI_DEV(0, 0x12, 0); + return __pci_0_12_0; } -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +void pci_ehci_dbg_set_port(const struct device *dev, unsigned int port) { u8 *base_regs = pci_ehci_base_regs(dev); u32 reg32; diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 46c151c..36b9209 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -1,38 +1,41 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ +#undef __SIMPLE_DEVICE__ #include <stdint.h> #include <device/pci_ops.h> #include <device/pci_ehci.h> #include <device/pci_def.h> -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +const struct device *pci_ehci_dbg_dev(void) { u32 class; - pci_devfn_t dev; + const struct device *dev; if (!CONFIG(HAVE_USBDEBUG_OPTIONS)) - return PCI_DEV(0, 0x1d, 7); + return __pci_0_1d_7; - if (hcd_idx == 2) - dev = PCI_DEV(0, 0x1a, 0); + if (CONFIG_USBDEBUG_HCD_INDEX == 2) + dev = __pci_0_19_0; else - dev = PCI_DEV(0, 0x1d, 0); + dev = __pci_0_1d_0; /* If we enter here before RCBA programming, EHCI function may * appear with the highest function number instead. */ class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; - if (class != PCI_EHCI_CLASSCODE) - dev |= PCI_DEV(0, 0, 7); + if (class != PCI_EHCI_CLASSCODE) { + if (CONFIG_USBDEBUG_HCD_INDEX == 2) + dev = NULL; + else + dev = __pci_0_1d_7; + } return dev; } /* Required for successful build, but currently empty. */ -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +void pci_ehci_dbg_set_port(const struct device *dev, unsigned int port) { /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/63387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea0598e01d8fc25b08fa8f22d0622ecc729e8160 Gerrit-Change-Number: 63387 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: Factor TI50/CR50 config
by Yu-Ping Wu (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Jes Klinke, Philipp Deppenwiese, Patrick Rudolph, Christian Walter, Werner Zeh. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63285 ) Change subject: Factor TI50/CR50 config ...................................................................... Patch Set 2: (5 comments) File src/drivers/tpm/Makefile.inc: https://review.coreboot.org/c/coreboot/+/63285/comment/1a8c4fe5_83cf473f PS2, Line 9: cr50.c I guess the next thing is to rename cr50-related files and folders? File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/c/coreboot/+/63285/comment/ef927929_48a43635 PS2, Line 387: if (CONFIG(CHROMEOS) && (!CONFIG(MAINBOARD_HAS_TPM_GSC))) Does Ti50 support ZTE? File src/vendorcode/google/chromeos/Kconfig: https://review.coreboot.org/c/coreboot/+/63285/comment/0e190082_11db4b12 PS2, Line 25: CR50 Also rename this? File src/vendorcode/google/chromeos/cse_board_reset.c: https://review.coreboot.org/c/coreboot/+/63285/comment/9c43bd08_2c9f6fec PS2, Line 41: /* : * Ti50 firmware of all versions support the above PLTRST wiring. : */ /* One line comment. */ https://review.coreboot.org/c/coreboot/+/63285/comment/6d6f6793_d4a880db PS2, Line 47: Remove extra blank line. -- To view, visit https://review.coreboot.org/c/coreboot/+/63285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I037b1b717a16c468e2f97a912da99f125b61e1ce Gerrit-Change-Number: 63285 Gerrit-PatchSet: 2 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jes Klinke <jbk(a)chromium.org> Gerrit-Attention: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 07:31:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Rex-BC Chen, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63251/comment/c0d45d5b_8251b5e8 PS5, Line 9: Add PCIe info to coreboot table. > As this is kind of a new “API”, please elaborate, why this information is needed now – and hasn’t on […] Done File payloads/libpayload/include/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/a0f91614_572eb99e PS4, Line 275: uint32_t > Use uint64_t for address? Done File payloads/libpayload/include/sysinfo.h: https://review.coreboot.org/c/coreboot/+/63251/comment/d471b3ad_e6944033 PS4, Line 87: struct { > Can we use the cb_pcie struct (just like the 'framebuffer' field below)? Then cb_parse_pcie() could […] Done, I use memcpy to fill the structure, I'm not sure which one is better, any suggestions? -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 6 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 07:30:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Jianjun Wang. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63251 to look at the new patch set (#6). Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... coreboot tables: Add PCIe info to coreboot table Add 'pcie_fill_lb' and 'lb_add_pcie' function to pass PCIe information through coreboot to libpayload. ARM platform usually does not have common address for PCIe to access the configuration space of devices, add new API to pass the base address of PCIe controller, configuration space and address translation space for libpayload to access PCIe devices. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c 6 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/63251/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 6 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Disable unused power
by Yu-Ping Wu (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Felix Singer, Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63247 ) Change subject: soc/mediatek/mt8186: Disable unused power ...................................................................... Patch Set 8: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63247/comment/b8ef980f_5f14bbed PS5, Line 9: NNA > It's a customer module, and we don't used it in drivers in coreboot for any Google Chrome projects. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c7c2d1b6a4c26980a3029b60051ab1406406ea Gerrit-Change-Number: 63247 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 07:07:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Initialize device_path subid
by 小田喜陽彦 (Code Review) 06 Apr '22

06 Apr '22

小田喜陽彦 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63384 ) Change subject: ec/google/chromeec: Initialize device_path subid ...................................................................... ec/google/chromeec: Initialize device_path subid Signed-off-by: Akihiko Odaki <akihiko.odaki(a)gmail.com> Change-Id: I910998a5555319cf9840493a31df4934054e08ce --- M src/ec/google/chromeec/ec_acpi.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/63384/1 diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 3d78128..7f94626 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -270,6 +270,7 @@ /* Set up a minimal EC0 device to pass to the DPTF helpers */ path.type = DEVICE_PATH_GENERIC; path.generic.id = 0; + path.generic.subid = 0; ec = alloc_find_dev(dev->bus, &path); ec->ops = &ec_ops; -- To view, visit https://review.coreboot.org/c/coreboot/+/63384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910998a5555319cf9840493a31df4934054e08ce Gerrit-Change-Number: 63384 Gerrit-PatchSet: 1 Gerrit-Owner: 小田喜陽彦 <akihiko.odaki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Disable unused power
by Rex-BC Chen (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Felix Singer, Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63247 ) Change subject: soc/mediatek/mt8186: Disable unused power ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63247/comment/fca51191_a2df992d PS5, Line 9: NNA > Explain what that means and what it is used for. It's a customer module, and we don't used it in drivers in coreboot for any Google Chrome projects. Therefore, I remove strings of NNA. Commit Message: https://review.coreboot.org/c/coreboot/+/63247/comment/0443f886_105c04bb PS7, Line 13: expeted > expected Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c7c2d1b6a4c26980a3029b60051ab1406406ea Gerrit-Change-Number: 63247 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 07:00:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Disable unused power
by Rex-BC Chen (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63247 to look at the new patch set (#8). Change subject: soc/mediatek/mt8186: Disable unused power ...................................................................... soc/mediatek/mt8186: Disable unused power To save the power consumption, we disable the unused power of optional components in coreboot. BUG=none TEST=the value of power consumption is as expected. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ic0c7c2d1b6a4c26980a3029b60051ab1406406ea --- M src/soc/mediatek/mt8186/include/soc/spm.h M src/soc/mediatek/mt8186/spm.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/63247/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/63247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c7c2d1b6a4c26980a3029b60051ab1406406ea Gerrit-Change-Number: 63247 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Disable unused power
by Yu-Ping Wu (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63247 ) Change subject: soc/mediatek/mt8186: Disable unused power ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63247/comment/13c23702_24443fba PS7, Line 13: expeted expected -- To view, visit https://review.coreboot.org/c/coreboot/+/63247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c7c2d1b6a4c26980a3029b60051ab1406406ea Gerrit-Change-Number: 63247 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 06:52:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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