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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62856/comment/51dd2356_7cf8e728
PS6, Line 641: s_cfg->UfsEnable[0] = 0; /* UFS Controller 0 is fuse disabled */
UFS is only support on ADL-N not P? I know eMMC, but is UFS universal or not?
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Hello build bot (Jenkins), Sean Rhodes, Michał Żygowski, Matt DeVillier, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: option: Allow to use the EFI variable driver as option backend
......................................................................
option: Allow to use the EFI variable driver as option backend
Use the introduced EFI variable store driver on top of the SMMSTORE region
in SPI flash to read/write options.
Change-Id: I520eca96bcd573f825ed35a29bf8f750e313a02d
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/Kconfig
A src/drivers/efi/option.c
2 files changed, 54 insertions(+), 0 deletions(-)
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Change subject: drivers/efi: Add EFI variable store option support
......................................................................
drivers/efi: Add EFI variable store option support
Add a driver to read and write EFI variables stored in a region device.
This is particullary useful for EDK2 as payload and allows to reuse
existing EFI tools to set/get options used by the firmware.
The write implementation is fault tolerant and doesn't corrupt the
variable store. A faulting write might result in using the old value
even though a 'newer' had been completely written.
Implemented basic unit tests for header corruption, writing existing data
and append new data into the store.
Initial firmware region state:
Initially the variable store region isn't formatted. Usually this is done
in the EDK2 payload when no valid firmware volume could be found.
It might be useful to do this offline or in coreboot to have a working
option store on the first boot or when it was corrupted.
Performance improvements:
Right now the code always checks if the firmware volume header is valid.
This could be optimised by caching the test result in heap. For write
operations it would be good to cache the end of the variable store in
the heap as well, instead of walking the whole store.
Reclaiming memory:
The EFI variable store is append write only. To update an existing
variable, first a new is written to the end of the store and then the
previous is marked invalid. This only works on PNOR flash that allow to
clear set bits, but keep cleared bits state.
This mechanisms allows a fault tolerant write, but it also requires to
"clean" the variable store for time to time. This cleaning would remove
variables that have been marked "deleted".
Such cleaning mechanism in turn must be fault tolerant and thus must use
a second parition in the SPI flash as backup/working region.
For now to cleaning is done in coreboot.
Fault checking:
The driver should check if a previous write was successfull and if not mark
variables as deleted on the next operation.
Tested and working:
- Could enumerate all existing variables
- Could read variables
- Could write variables
Change-Id: I8079f71d29da5dc2db956fc68bef1486fe3906bb
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
A src/drivers/efi/Kconfig
A src/drivers/efi/Makefile.inc
A src/drivers/efi/efivars.c
A src/drivers/efi/efivars.h
M tests/Makefile.inc
A tests/drivers/Makefile.inc
A tests/drivers/efivars.c
7 files changed, 880 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/52564/12
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Change subject: mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMI
......................................................................
Patch Set 8:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63366/comment/af09fd28_ed642761
PS8, Line 7: /
> and (or remove the spaces around the slash)
Done
https://review.coreboot.org/c/coreboot/+/63366/comment/70a87a45_184eba25
PS8, Line 7: Type-C / HDMI
> Or: either Type-C or HDMI
Done
https://review.coreboot.org/c/coreboot/+/63366/comment/6902f928_abe0b617
PS8, Line 17: HDMI: TypeCPort2Config = "DP Fixed Connection"
> Which of the two works by default?
Not sure if I understand what you mean. Currently we have it set to "No Thunderbolt" by default. But that's arbitrary, we could have chosen either one.
File src/mainboard/google/brya/variants/nereid/variant.c:
https://review.coreboot.org/c/coreboot/+/63366/comment/fbbabdaf_12c85182
PS8, Line 36: BIOS_DEBUG
> Could be info?
Done
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMI
......................................................................
mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMI
Some bytes in the descriptor need to be set differently for Type-C and
HDMI. To allow using a single firmware variant for both cases, update
the descriptor at runtime based on fw_config. This is a temporary
workaround while we find a better solution.
The byte values were determined by changing the following CSE strap and
comparing the generated descriptors:
Type-C: TypeCPort2Config = "No Thunderbolt"
HDMI: TypeCPort2Config = "DP Fixed Connection"
BUG=b:226848617
TEST=Type-C and HDMI both work on nereid with fw_config set correctly.
Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e
Signed-off-by: Reka Norman <rekanorman(a)google.com>
---
A '
M src/mainboard/google/brya/Kconfig.name
M src/mainboard/google/brya/bootblock.c
M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/brya/variants/nereid/Makefile.inc
M src/mainboard/google/brya/variants/nereid/variant.c
6 files changed, 78 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/63366/9
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Change subject: soc/intel/alderlake: Add support to update descriptor at runtime
......................................................................
Patch Set 8:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63365/comment/1a692567_9dd804cb
PS7, Line 10: following
> follow-up
Done
File src/soc/intel/alderlake/bootblock/update_descriptor.c:
https://review.coreboot.org/c/coreboot/+/63365/comment/befbae98_9161de30
PS7, Line 22: host(Flash Master 1)
> Please add a space before the (.
Done
https://review.coreboot.org/c/coreboot/+/63365/comment/3ac98478_e711f9f8
PS7, Line 23: int
> Use bool?
Done
https://review.coreboot.org/c/coreboot/+/63365/comment/3abbe418_5e95c597
PS7, Line 27: BIOS_DEBUG
> Should be an error?
Done
https://review.coreboot.org/c/coreboot/+/63365/comment/ff290e2f_f823f66d
PS7, Line 33: printk(BIOS_DEBUG, "Host doesn't have write access to Descriptor Region\n");
> Ditto.
Done
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Add support to update descriptor at runtime
......................................................................
soc/intel/alderlake: Add support to update descriptor at runtime
On nereid, we need to update the descriptor based on fw_config (see
the follow-up patch), so add support to update the descriptor at
runtime. This is a temporary workaround while we find a better solution.
This is basically adding back the configure_pmc_descriptor() function
removed in CB:63339, just making it generic and allowing it to update
multiple bytes at once.
BUG=b:226848617
TEST=With the following patch, Type-C and HDMI work on nereid.
Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe
Signed-off-by: Reka Norman <rekanorman(a)google.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/Makefile.inc
A src/soc/intel/alderlake/bootblock/update_descriptor.c
M src/soc/intel/alderlake/include/soc/bootblock.h
4 files changed, 107 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/63365/8
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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
soc/intel/alderlake: Add support for UFS controller
UFS (Universal Flash Storage) is the next generation storage
standard and a SCSI storage technology. It is also a successor
of eMMC.
Following changes are needed to add support for UFS in ADL-N.
1) Add UFS controller to chipset.cb and keep it off by default
2) Hook up FSP enable UPD for UFS #1 to the device from chipset.cb
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4
---
M src/soc/intel/alderlake/chipset.cb
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/62856/6
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