coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: mb/google/brya/var/vell: Remove Rcomp settings
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62201 ) Change subject: mb/google/brya/var/vell: Remove Rcomp settings ...................................................................... mb/google/brya/var/vell: Remove Rcomp settings This patch removes Rcomp settings. In MRC design, it checks if the Rcomp settings from the board is 0 or null, if so, it uses the recommended Rcomp values. Otherwise, it uses the Rcomp settings passed from the UPD. From the change history of MRC, we're chasing a moving target. This RCOMP setting in coreboot is an old setting while the Rcomp settins in MRC are optimized settings. Moving forward, if there is a new stepping, it might be changed again which increases the maintenance effort in coreboot. IMHO, we should let MRC to set the optimized RCOMP values for the design. BUG=b:219378758 TEST=emerge-byra coreboot chromeos-bootimage and boots up with QS and PRQ CPUs. Checks with MRC log and ensure the RCOMP settings are filled properly by MRC. Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62201 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/vell/memory.c 1 file changed, 1 insertion(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/vell/memory.c b/src/mainboard/google/brya/variants/vell/memory.c index fd36c5d..faa6eec 100644 --- a/src/mainboard/google/brya/variants/vell/memory.c +++ b/src/mainboard/google/brya/variants/vell/memory.c @@ -8,13 +8,7 @@ static const struct mb_cfg baseboard_memcfg = { .type = MEM_TYPE_LP5X, - .rcomp = { - /* Baseboard uses only 100ohm Rcomp resistors */ - .resistor = 100, - - /* Baseboard Rcomp target values */ - .targets = { 40, 36, 35, 35, 35 }, - }, + /* Leave Rcomp unspecified to use the FSP optimized defaults */ /* DQ byte map */ .lpx_dq_map = { -- To view, visit https://review.coreboot.org/c/coreboot/+/62201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb Gerrit-Change-Number: 62201 Gerrit-PatchSet: 4 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: sb/intel/lynxpoint: Fix up comment
by Marina Michelle (Code Review) 02 Mar '22

02 Mar '22

Marina Michelle has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/62342 ) Change subject: sb/intel/lynxpoint: Fix up comment ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/62342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie46b63d192b8e4871442f6b0db5b1575168f89ce Gerrit-Change-Number: 62342 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: revert

1 0

Change in coreboot[master]: Revert "sb/intel/lynxpoint: Fix up comment"
by Marina Michelle (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Angel Pons, Lean Sheng Tan, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Angel Pons, Lean Sheng Tan, Patrick Rudolph, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62522 to review the following change. Change subject: Revert "sb/intel/lynxpoint: Fix up comment" ...................................................................... Revert "sb/intel/lynxpoint: Fix up comment" This reverts commit 0cd1a87d50177a9f6ad912e934ad5d918a952109. Reason for revert: <INSERT REASONING HERE> Not running. Change-Id: I87c7c27abf36e5f4b0c1a3aded75bc92ba9a2e7c --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/62522/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 71ce080..ea84def 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -691,8 +691,8 @@ int index) { /* - * Check if the register is enabled. If so, and the base exceeds the - * device's default claim range, add the resource. + * Check if the register is enabled. If so and the base exceeds the + * device's default, claim range and add the resource. */ if (reg_value & 1) { u16 base = reg_value & 0xfffc; -- To view, visit https://review.coreboot.org/c/coreboot/+/62522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87c7c27abf36e5f4b0c1a3aded75bc92ba9a2e7c Gerrit-Change-Number: 62522 Gerrit-PatchSet: 1 Gerrit-Owner: Marina Michelle <marinamichelle100(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/glados: Restore ChromeEC tablet mode switch for caroline, cave
by Angel Pons (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Matt DeVillier, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62447 ) Change subject: mb/google/glados: Restore ChromeEC tablet mode switch for caroline, cave ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62447/comment/2debf40a_e5350ca5 PS1, Line 9: Commit 017b5c45 [ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT config] nit: wrap lines at 72 characters. See CB:60006 -- To view, visit https://review.coreboot.org/c/coreboot/+/62447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0ae5b6a61f104b5e973383344d289cc2e2a7b8d Gerrit-Change-Number: 62447 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 02 Mar 2022 13:08:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
by Yu-Ping Wu (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62472 ) Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Gerrit-Change-Number: 62472 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 02 Mar 2022 12:54:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO driving functions
by Yu-Ping Wu (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62471 ) Change subject: soc/mediatek/mt8186: Add GPIO driving functions ...................................................................... Patch Set 4: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62471/comment/4e434ac1_fb70bd47 PS4, Line 11: from different SoCs for each SoC https://review.coreboot.org/c/coreboot/+/62471/comment/52d770e8_0dc37511 PS4, Line 11: Value The value -- To view, visit https://review.coreboot.org/c/coreboot/+/62471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Gerrit-Change-Number: 62471 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 02 Mar 2022 12:52:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support
by build bot (Jenkins) (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Michał Żygowski. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support ...................................................................... Patch Set 2: Verified-1 (1 comment) File src/mainboard/clevo/tgl-u/bootblock.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142913): https://review.coreboot.org/c/coreboot/+/62498/comment/1f8bd9f6_c2c9da33 PS2, Line 14: static void dgpu_power_enable(int onoff) { open brace '{' following function definitions go on the next line -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 11:56:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3
by build bot (Jenkins) (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Michał Kopeć. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62496 ) Change subject: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3 ...................................................................... Patch Set 2: Verified-1 (1 comment) File src/drivers/gfx/nvidia/optimus/optimus.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142911): https://review.coreboot.org/c/coreboot/+/62496/comment/e7cabef6_8b6d64e8 PS2, Line 261: const struct opregion rp_pci_config = OPREGION("PXCS", SYSTEMMEMORY, CONFIG_ECAM_MMCONF_BASE_ADDRESS | (parent->path.pci.devfn << 12), 0x1000); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/62496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bc6ec7a6a3e18417537b1f092a29972e9875282 Gerrit-Change-Number: 62496 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 11:53:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload/bin/lpgcc: Make lpgcc provide TPM configuration for vboot
by Jakub Czapiga (Code Review) 02 Mar '22

02 Mar '22

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62516 ) Change subject: libpayload/bin/lpgcc: Make lpgcc provide TPM configuration for vboot ...................................................................... libpayload/bin/lpgcc: Make lpgcc provide TPM configuration for vboot TPM1_MODE and TPM2_MODE defines have to be added to vboot and payload cflags to make them build correctly without requiring payloads to provide defines. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I567a9f04d7089699840dc7e0a063cf3030fb934b --- M payloads/libpayload/bin/lpgcc 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/62516/1 diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 8bc46a6..77ceda3 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -182,6 +182,14 @@ _CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h" _CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include" +if [ "$CONFIG_LP_VBOOT_LIB" = y ]; then + if [ "$CONFIG_LP_VBOOT_TPM2_MODE" = y ]; then + _CFLAGS="$_CFLAGS -DTPM2_MODE" + else + _CFLAGS="$_CFLAGS -DTPM1_MODE" + fi +fi + _LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static -Wl,--gc-sections" if [ $DOLINK -eq 0 ]; then -- To view, visit https://review.coreboot.org/c/coreboot/+/62516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I567a9f04d7089699840dc7e0a063cf3030fb934b Gerrit-Change-Number: 62516 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: src/driver/wifi: Add _DSM method for DDRRFIM
by Varshit B Pandya (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Rizwan Qureshi, Sugnan Prabhu S. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61020 ) Change subject: src/driver/wifi: Add _DSM method for DDRRFIM ...................................................................... Patch Set 18: (5 comments) File src/drivers/wifi/generic/acpi.c: https://review.coreboot.org/c/coreboot/+/61020/comment/df1f7da1_e85aa868 PS16, Line 40: bool is_cnviDdrRfim_enabled = false; > I don't think we need to make this variable a global, see below. Done https://review.coreboot.org/c/coreboot/+/61020/comment/80a5410d_e0422175 PS16, Line 160: acpigen_write_return_integer(is_cnviDdrRfim_enabled); > with my suggestions from below, this would now look like […] Done https://review.coreboot.org/c/coreboot/+/61020/comment/09724d6c_5b0fbdcb PS16, Line 540: is_cnviDdrRfim_enabled = config->enable_cnvi_ddr_rfim; > with suggestions, this is now a local variable Done https://review.coreboot.org/c/coreboot/+/61020/comment/521e0a96_87f9d9f1 PS16, Line 607: NULL > In order to avoid having `is_cnviDdrRfim_enabled` as a global variable, I think you can make it a lo […] Done https://review.coreboot.org/c/coreboot/+/61020/comment/14e46007_4858a236 PS16, Line 649: wifi_ssdt_write_properties(dev, path); > I think instead we should pass the `generic` device here or at least grab the CNVi property here, e. […] I put some prints and saw that wifi_pcie_fill_ssdt is getting called and wifi_cnvi_fill_ssdt is not called. probably this is because wifi_generic_enable is not getting called in generic.c the ops are getting assigned from generic pci driver. -- To view, visit https://review.coreboot.org/c/coreboot/+/61020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37 Gerrit-Change-Number: 61020 Gerrit-PatchSet: 18 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 11:25:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022