coreboot-gerrit March 2022

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Change in coreboot[master]: libpayload: cbmem_console: Drop loglevel markers from snapshot
by Yu-Ping Wu (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Raul Rangel, Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62506 ) Change subject: libpayload: cbmem_console: Drop loglevel markers from snapshot ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62506/comment/82b93ab1_ab3168da PS1, Line 9: recently CB:61308 for my own reference File payloads/libpayload/drivers/cbmem_console.c: https://review.coreboot.org/c/coreboot/+/62506/comment/39ba1777_769b23a6 PS1, Line 120: /* Slight memory corruption may occur between reboots and give us a few : unprintable characters like '\0'. Replace them with '?' on output. */ : for (cursor = 0; cursor < size; cursor++) : if (!isprint(console_c[cursor]) && !isspace(console_c[cursor])) : console_c[cursor] = '?'; Maybe we should just keep the non-printable characters, and let payloads decide how to deal with them. For that we'll need to add BIOS_LOG_IS_MARKER and friends to libpayload.h (will that cause licensing issue?). What do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/62506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a9e5d464508320cf43ea572d62896d38c2a128d Gerrit-Change-Number: 62506 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 02 Mar 2022 13:50:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: skip heci_init() if HECI1 is disabled
by Marina Michelle (Code Review) 02 Mar '22

02 Mar '22

Marina Michelle has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/61407 ) Change subject: soc/intel/common/cse: skip heci_init() if HECI1 is disabled ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/61407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0babe417173d10e37327538dc9e7aae980225367 Gerrit-Change-Number: 61407 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: revert

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Change in coreboot[master]: Revert "soc/intel/common/cse: skip heci_init() if HECI1 is disabled"
by Marina Michelle (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Subrata Banik, Matt DeVillier, Tim Wawrzynczak, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Subrata Banik, Matt DeVillier, Tim Wawrzynczak, Patrick Rudolph, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62524 to review the following change. Change subject: Revert "soc/intel/common/cse: skip heci_init() if HECI1 is disabled" ...................................................................... Revert "soc/intel/common/cse: skip heci_init() if HECI1 is disabled" This reverts commit f711bf03a694bc594a610a70251716d425fbe101. Reason for revert: <INSERT REASONING HERE> Not running Change-Id: I67433336959e23e7b12afa4978f02ec928f4bb36 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/62524/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 32f6d4f..7d6faba 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -94,10 +94,6 @@ u16 pcireg; - /* Check if device enabled */ - if (!is_cse_enabled()) - return; - /* Assume it is already initialized, nothing else to do */ if (get_cse_bar(dev)) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/62524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67433336959e23e7b12afa4978f02ec928f4bb36 Gerrit-Change-Number: 62524 Gerrit-PatchSet: 1 Gerrit-Owner: Marina Michelle <marinamichelle100(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: crossgcc: Upgrade binutils from 2.37 to 2.38
by Elyes Haouas (Code Review) 02 Mar '22

02 Mar '22

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/61767 ) Change subject: crossgcc: Upgrade binutils from 2.37 to 2.38 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/61767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94a11e52be878b13eae9f00f7d6dc1ab2053693e Gerrit-Change-Number: 61767 Gerrit-PatchSet: 13 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
by Arthur Heymans (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Arthur Heymans, Anil Kumar K, Subrata Banik, Tim Wawrzynczak, Paul Menzel, Andrey Petrov, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59638 ) Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2 ...................................................................... Patch Set 38: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/util.h: https://review.coreboot.org/c/coreboot/+/59638/comment/c87e6b25_da8b46ea PS38, Line 34: __packed Drop this. Datatypes should align: 2 x uint64_t -- To view, visit https://review.coreboot.org/c/coreboot/+/59638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Gerrit-Change-Number: 59638 Gerrit-PatchSet: 38 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Mar 2022 13:34:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "soc/intel/common/block/cse: move cse_disable_mei_devices() in...
by Angel Pons (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Subrata Banik, Matt DeVillier, Paul Menzel, Marina Michelle, Patrick Rudolph, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62523 ) Change subject: Revert "soc/intel/common/block/cse: move cse_disable_mei_devices() into disable_heci.c" ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62523/comment/e7b9eef9_192aa3e2 PS1, Line 12: Not running Please elaborate. -- To view, visit https://review.coreboot.org/c/coreboot/+/62523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifab2dc957a83106b0c777b61297e605cbf607759 Gerrit-Change-Number: 62523 Gerrit-PatchSet: 1 Gerrit-Owner: Marina Michelle <marinamichelle100(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marina Michelle <marinamichelle100(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Mar 2022 13:22:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/cs35l53: Add driver for generating device in SSDT
by Angel Pons (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Patrick Georgi, Furquan Shaikh, Subrata Banik, Vitaly Rodionov, Paul Menzel, Nick Vaccaro, Robert Chen, Marco Chen, Name of user not set #1004174, Karthik Ramasubramanian, Xiang Liu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61448 ) Change subject: drivers/i2c/cs35l53: Add driver for generating device in SSDT ...................................................................... Patch Set 6: (1 comment) File src/drivers/i2c/cs35l53/chip.h: https://review.coreboot.org/c/coreboot/+/61448/comment/ca7c19d5_fa85634c PS6, Line 128: enum cs35l53_gpio_src gpio_src_select[CS35L53_MAX_GPIOS]; > > We made the change to using arrays in response to a suggestion from Subrata Banik. I wouldn't want to change this back without agreement from them. > > The reason, I have suggested an array to have flexibility to have more GPIOx if required in future. Does this chip have any other GPIOs? I don't have any datasheets to check. > Additionally, https://review.coreboot.org/c/coreboot/+/61448/6/src/drivers/i2c/cs35l53/cs… can better handle using `loop` isn't it ? I wouldn't use a loop if there's only 2 GPIOs, especially for settings that aren't the same for both GPIOs. -- To view, visit https://review.coreboot.org/c/coreboot/+/61448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cbb1cef89f8d56ee73fab06c68933a2ab8c3606 Gerrit-Change-Number: 61448 Gerrit-PatchSet: 6 Gerrit-Owner: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Name of user not set #1004174 Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Vitaly Rodionov <vitaly.rodionov(a)gmail.com> Gerrit-CC: Xiang Liu <xiang.liu(a)cirrus.corp-partner.google.com> Gerrit-CC: YH Lin <yueherngl(a)chromium.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Name of user not set #1004174 Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Xiang Liu <xiang.liu(a)cirrus.corp-partner.google.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 13:20:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Name of user not set #1004174 Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: move cse_disable_mei_devices() into disab...
by Marina Michelle (Code Review) 02 Mar '22

02 Mar '22

Marina Michelle has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/61881 ) Change subject: soc/intel/common/block/cse: move cse_disable_mei_devices() into disable_heci.c ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/61881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee6aff570aa4465ced6ffe2968412bcbb5ff3a8d Gerrit-Change-Number: 61881 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: revert

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Change in coreboot[master]: Revert "soc/intel/common/block/cse: move cse_disable_mei_devices() in...
by Marina Michelle (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Subrata Banik, Matt DeVillier, Paul Menzel, Angel Pons, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Subrata Banik, Matt DeVillier, Paul Menzel, Angel Pons, Patrick Rudolph, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62523 to review the following change. Change subject: Revert "soc/intel/common/block/cse: move cse_disable_mei_devices() into disable_heci.c" ...................................................................... Revert "soc/intel/common/block/cse: move cse_disable_mei_devices() into disable_heci.c" This reverts commit 148b5456715cc8eebd25878c67ce906b6fc3adce. Reason for revert: <INSERT REASONING HERE> Not running Change-Id: Ifab2dc957a83106b0c777b61297e605cbf607759 --- M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/cse/disable_heci.c 2 files changed, 19 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/62523/1 diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 0f1d6ca..c17e227 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -10,6 +10,10 @@ #include <timestamp.h> #include <types.h> +#define PMC_IPC_MEI_DISABLE_ID 0xa9 +#define PMC_IPC_MEI_DISABLE_SUBID_ENABLE 0 +#define PMC_IPC_MEI_DISABLE_SUBID_DISABLE 1 + enum cse_eop_result { CSE_EOP_RESULT_GLOBAL_RESET_REQUESTED, CSE_EOP_RESULT_SUCCESS, @@ -46,6 +50,21 @@ return true; } +bool cse_disable_mei_devices(void) +{ + struct pmc_ipc_buffer req = { 0 }; + struct pmc_ipc_buffer rsp; + uint32_t cmd; + + cmd = pmc_make_ipc_cmd(PMC_IPC_MEI_DISABLE_ID, PMC_IPC_MEI_DISABLE_SUBID_DISABLE, 0); + if (pmc_send_ipc_cmd(cmd, &req, &rsp) != CB_SUCCESS) { + printk(BIOS_ERR, "CSE: Failed to disable MEI devices\n"); + return false; + } + + return true; +} + static enum cse_eop_result cse_send_eop(void) { enum { diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c index 84a09fd..ab8b3ad 100644 --- a/src/soc/intel/common/block/cse/disable_heci.c +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -10,7 +10,6 @@ #include <intelblocks/cse.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> -#include <intelblocks/pmc_ipc.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> @@ -18,31 +17,12 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -#define PMC_IPC_MEI_DISABLE_ID 0xa9 -#define PMC_IPC_MEI_DISABLE_SUBID_ENABLE 0 -#define PMC_IPC_MEI_DISABLE_SUBID_DISABLE 1 - /* Disable HECI using PCR */ static void heci1_disable_using_pcr(void) { soc_disable_heci1_using_pcr(); } -bool cse_disable_mei_devices(void) -{ - struct pmc_ipc_buffer req = { 0 }; - struct pmc_ipc_buffer rsp; - uint32_t cmd; - - cmd = pmc_make_ipc_cmd(PMC_IPC_MEI_DISABLE_ID, PMC_IPC_MEI_DISABLE_SUBID_DISABLE, 0); - if (pmc_send_ipc_cmd(cmd, &req, &rsp) != CB_SUCCESS) { - printk(BIOS_ERR, "CSE: Failed to disable MEI devices\n"); - return false; - } - - return true; -} - /* Disable HECI using PMC IPC communication */ static void heci1_disable_using_pmc(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/62523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifab2dc957a83106b0c777b61297e605cbf607759 Gerrit-Change-Number: 62523 Gerrit-PatchSet: 1 Gerrit-Owner: Marina Michelle <marinamichelle100(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
by Marina Michelle (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Marina Michelle has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62472 ) Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Rub -- To view, visit https://review.coreboot.org/c/coreboot/+/62472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Gerrit-Change-Number: 62472 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marina Michelle <marinamichelle100(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 02 Mar 2022 13:18:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2022