coreboot-gerrit March 2022

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Change in coreboot[master]: device/pci_device.c: Improve pci_bridge_route() readability
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59131 ) Change subject: device/pci_device.c: Improve pci_bridge_route() readability ...................................................................... device/pci_device.c: Improve pci_bridge_route() readability Both the secondary and subordinate bus numbers are configured in this function but it's not easy to search for in the tree as the PCI writes are hidden inside a bigger write to 'PCI_PRIMARY_BUS'. Use separate variables and PCI config writes to improve the readability. Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59131 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/pci_device.c 1 file changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 82494b9..22ccf59 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1499,7 +1499,7 @@ { struct device *dev = link->dev; struct bus *parent = dev->bus; - u32 reg, buses = 0; + uint8_t primary, secondary, subordinate; if (state == PCI_ROUTE_SCAN) { link->secondary = parent->subordinate + 1; @@ -1507,15 +1507,17 @@ } if (state == PCI_ROUTE_CLOSE) { - buses |= 0xfeff << 8; + primary = 0; + secondary = 0xff; + subordinate = 0xfe; } else if (state == PCI_ROUTE_SCAN) { - buses |= parent->secondary & 0xff; - buses |= ((u32) link->secondary & 0xff) << 8; - buses |= 0xff << 16; /* MAX PCI_BUS number here */ + primary = parent->secondary; + secondary = link->secondary; + subordinate = 0xff; /* MAX PCI_BUS number here */ } else if (state == PCI_ROUTE_FINAL) { - buses |= parent->secondary & 0xff; - buses |= ((u32) link->secondary & 0xff) << 8; - buses |= ((u32) link->subordinate & 0xff) << 16; + primary = parent->secondary; + secondary = link->secondary; + subordinate = link->subordinate; } if (state == PCI_ROUTE_SCAN) { @@ -1530,11 +1532,9 @@ * transactions will not be propagated by the bridge if it is not * correctly configured. */ - - reg = pci_read_config32(dev, PCI_PRIMARY_BUS); - reg &= 0xff000000; - reg |= buses; - pci_write_config32(dev, PCI_PRIMARY_BUS, reg); + pci_write_config8(dev, PCI_PRIMARY_BUS, primary); + pci_write_config8(dev, PCI_SECONDARY_BUS, secondary); + pci_write_config8(dev, PCI_SUBORDINATE_BUS, subordinate); if (state == PCI_ROUTE_FINAL) { pci_write_config16(dev, PCI_COMMAND, link->bridge_cmd); -- To view, visit https://review.coreboot.org/c/coreboot/+/59131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9 Gerrit-Change-Number: 59131 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "sb/intel/lynxpoint: Fix up comment"
by Angel Pons (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Marina Michelle, Lean Sheng Tan, Patrick Rudolph, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62522 ) Change subject: Revert "sb/intel/lynxpoint: Fix up comment" ...................................................................... Patch Set 1: Code-Review-2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62522/comment/ae56d3f3_65773a58 PS1, Line 12: Not running. Um, this change simply updates a comment. How does reverting it help? -- To view, visit https://review.coreboot.org/c/coreboot/+/62522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87c7c27abf36e5f4b0c1a3aded75bc92ba9a2e7c Gerrit-Change-Number: 62522 Gerrit-PatchSet: 1 Gerrit-Owner: Marina Michelle <marinamichelle100(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marina Michelle <marinamichelle100(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Mar 2022 13:13:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62290 ) Change subject: soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test ...................................................................... soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test The XTAL 26MHz test failed on krabby, so we adjust RTC capid from default value 0x88 to 0xC0 for MT8186. We also add a new log message to show the capid value which is read from MT6366. This implementation is according to chapter 5.13 in MT8186 Functional Specification. BUG=b:218439447 TEST=set capid to 0xc0. TEST=XTAL 26MHz test passed. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62290 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/include/soc/rtc.h M src/soc/mediatek/mt8186/rtc.c 2 files changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/include/soc/rtc.h b/src/soc/mediatek/mt8186/include/soc/rtc.h index 3a0c7cd..a3fb7a0 100644 --- a/src/soc/mediatek/mt8186/include/soc/rtc.h +++ b/src/soc/mediatek/mt8186/include/soc/rtc.h @@ -143,6 +143,7 @@ PMIC_RG_DCXO_CW00 = 0x0788, PMIC_RG_DCXO_CW00_CLR = 0x078C, PMIC_RG_DCXO_CW02 = 0x0790, + PMIC_RG_DCXO_CW03 = 0x0794, PMIC_RG_DCXO_CW07 = 0x079A, PMIC_RG_DCXO_CW09 = 0x079E, PMIC_RG_DCXO_CW11 = 0x07A2, diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c index 528f42b..2f78be8 100644 --- a/src/soc/mediatek/mt8186/rtc.c +++ b/src/soc/mediatek/mt8186/rtc.c @@ -13,6 +13,8 @@ #include <soc/pmic_wrap.h> #include <timer.h> +#define MT8186_RTC_DXCO_CAPID 0xC0 + /* Initialize RTC setting of using DCXO clock */ static bool rtc_enable_dcxo(void) { @@ -231,6 +233,16 @@ rtc_write(PMIC_RG_DCXO_CW23, 0x0052); } +static void rtc_set_capid(u16 capid) +{ + u16 read_capid; + + rtc_write(PMIC_RG_DCXO_CW03, 0xFF00 | capid); + + rtc_read(PMIC_RG_DCXO_CW03, &read_capid); + rtc_info("read back capid: %#x\n", read_capid & 0xFF); +} + /* Check RTC Initialization */ int rtc_init(int recover) { @@ -337,6 +349,8 @@ rtc_write(PMIC_RG_DCXO_CW09, 0x408F); mdelay(5); + rtc_set_capid(MT8186_RTC_DXCO_CAPID); + mt6366_dcxo_disable_unused(); } 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282 Gerrit-Change-Number: 62290 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: remove unused RTC_GPIO_USER_MASK
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62457 ) Change subject: soc/mediatek: remove unused RTC_GPIO_USER_MASK ...................................................................... soc/mediatek: remove unused RTC_GPIO_USER_MASK RTC_GPIO_USER_MASK is not used in any drivers, so we remove them. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62457 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/rtc_mt6359p.c M src/soc/mediatek/mt8173/rtc.c M src/soc/mediatek/mt8183/rtc.c M src/soc/mediatek/mt8186/rtc.c 4 files changed, 0 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/rtc_mt6359p.c b/src/soc/mediatek/common/rtc_mt6359p.c index b5c381b..2b5611b 100644 --- a/src/soc/mediatek/common/rtc_mt6359p.c +++ b/src/soc/mediatek/common/rtc_mt6359p.c @@ -9,8 +9,6 @@ #include <soc/rtc_common.h> #include <timer.h> -#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) - static struct pmif *pmif_arb = NULL; void rtc_read(u16 addr, u16 *rdata) diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index d60f722..326a951 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -7,8 +7,6 @@ #include <soc/pmic_wrap.h> #include <types.h> -#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) - /* initialize rtc related gpio */ static bool rtc_gpio_init(void) { diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index e90aa9d..40830b0 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -8,8 +8,6 @@ #include <soc/pmic_wrap.h> #include <timer.h> -#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) - /* initialize rtc setting of using dcxo clock */ static bool rtc_enable_dcxo(void) { diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c index 7e38742..528f42b 100644 --- a/src/soc/mediatek/mt8186/rtc.c +++ b/src/soc/mediatek/mt8186/rtc.c @@ -13,8 +13,6 @@ #include <soc/pmic_wrap.h> #include <timer.h> -#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) - /* Initialize RTC setting of using DCXO clock */ static bool rtc_enable_dcxo(void) { 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd Gerrit-Change-Number: 62457 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork: fix SMMSTORE size, alignment in default FMAP
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Raul Rangel, Matt DeVillier, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62443 ) Change subject: mb/google/zork: fix SMMSTORE size, alignment in default FMAP ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: adding Raul and Karthik to make them aware of this change -- To view, visit https://review.coreboot.org/c/coreboot/+/62443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied04e93379e1507f5e6b2a1b71e4098a4561e5d8 Gerrit-Change-Number: 62443 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 13:12:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: enable the SPD_CACHE_ENABLE
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62296 ) Change subject: mb/google/brya: enable the SPD_CACHE_ENABLE ...................................................................... mb/google/brya: enable the SPD_CACHE_ENABLE google/brask is using SODIMMs for DRAM. Reading spd data is surprisingly slow (~170 ms), therefore enable the SPD cache. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=run on the device and measure the boot time decrease. Change-Id: If0a0072160a48b607ad17c0a1819ab49eaad92db Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62296 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index f7bd715..00e8bc9 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -239,6 +239,7 @@ config MEMORY_SODIMM def_bool n + select SPD_CACHE_ENABLE select SPD_CACHE_IN_FMAP config MEMORY_SOLDERDOWN -- To view, visit https://review.coreboot.org/c/coreboot/+/62296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0a0072160a48b607ad17c0a1819ab49eaad92db Gerrit-Change-Number: 62296 Gerrit-PatchSet: 6 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants: add the smbus addr for dimm1
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62295 ) Change subject: mb/google/brya/variants: add the smbus addr for dimm1 ...................................................................... mb/google/brya/variants: add the smbus addr for dimm1 Align the setting with the adlrvp BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and works correctly in the brask Change-Id: Ia4c889e7dd065632e180cf983c7c5ece0c461edd Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62295 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/brask/memory.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/memory.c b/src/mainboard/google/brya/variants/baseboard/brask/memory.c index 2e24110..447328b 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/memory.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/memory.c @@ -39,5 +39,7 @@ { spd_info->topo = MEM_TOPO_DIMM_MODULE; spd_info->smbus[0].addr_dimm[0] = 0x50; + spd_info->smbus[0].addr_dimm[1] = 0x51; spd_info->smbus[1].addr_dimm[0] = 0x52; + spd_info->smbus[1].addr_dimm[1] = 0x53; } 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4c889e7dd065632e180cf983c7c5ece0c461edd Gerrit-Change-Number: 62295 Gerrit-PatchSet: 6 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb, soc: Add the SPD_CACHE_ENABLE
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62294 ) Change subject: mb, soc: Add the SPD_CACHE_ENABLE ...................................................................... mb, soc: Add the SPD_CACHE_ENABLE In order to cache the spd data which reads from the memory module, we add SPD_CACHE_ENABLE option to enable the cache for the spd data. If this option is enabled, the RW_SPD_CACHE region needs to be added to the flash layout for caching the data. Since the user may remove the memory module after the bios caching the data, we need to add the invalidate flag to invalidate the mrc cache. Otherwise, the bios will use the mrc cache and can make the device malfunction. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and enable this feature to the brask the device could speed up around 150ms with this feature. Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294 Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/romstage.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/shadowmountain/romstage.c M src/mainboard/prodrive/atlas/romstage_fsp_params.c M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c M src/soc/intel/common/block/include/intelblocks/meminit.h M src/soc/intel/common/block/memory/Kconfig M src/soc/intel/common/block/memory/meminit.c M src/soc/intel/tigerlake/meminit.c 10 files changed, 80 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/romstage.c b/src/mainboard/google/brya/romstage.c index ae47167..a00cf32 100644 --- a/src/mainboard/google/brya/romstage.c +++ b/src/mainboard/google/brya/romstage.c @@ -13,6 +13,7 @@ const struct mb_cfg *mem_config = variant_memory_params(); bool half_populated = variant_is_half_populated(); struct mem_spd spd_info; + bool dimms_changed = false; memset(&spd_info, 0, sizeof(spd_info)); variant_get_spd_info(&spd_info); @@ -20,7 +21,11 @@ const struct pad_config *pads; size_t pads_num; - memcfg_init(m_cfg, mem_config, &spd_info, half_populated); + memcfg_init(m_cfg, mem_config, &spd_info, half_populated, &dimms_changed); + if (dimms_changed) { + memupd->FspmArchUpd.NvsBufferPtr = 0; + memupd->FspmArchUpd.BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; + } pads = variant_romstage_gpio_table(&pads_num); gpio_configure_pads(pads, pads_num); diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index a0453ef..5b5cc6b 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -48,6 +48,7 @@ const struct mb_cfg *mem_config = variant_memory_params(); int board_id = get_board_id(); const bool half_populated = false; + bool dimms_changed = false; const struct mem_spd memory_down_spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, @@ -72,7 +73,8 @@ case ADL_P_DDR4_1: case ADL_P_DDR4_2: case ADL_P_DDR5_1: - memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated); + memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated, + &dimms_changed); break; case ADL_P_DDR5_2: case ADL_P_LP4_1: @@ -82,7 +84,8 @@ case ADL_M_LP4: case ADL_M_LP5: case ADL_N_LP5: - memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated); + memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated, + &dimms_changed); break; default: die("Unknown board id = 0x%x\n", board_id); diff --git a/src/mainboard/intel/shadowmountain/romstage.c b/src/mainboard/intel/shadowmountain/romstage.c index 48c20db..0951936 100644 --- a/src/mainboard/intel/shadowmountain/romstage.c +++ b/src/mainboard/intel/shadowmountain/romstage.c @@ -12,11 +12,12 @@ FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; const struct mb_cfg *mem_config = variant_memory_params(); const bool half_populated = false; + bool dimms_changed = false; const struct mem_spd lp5_spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, .cbfs_index = variant_memory_sku(), }; - memcfg_init(m_cfg, mem_config, &lp5_spd_info, half_populated); + memcfg_init(m_cfg, mem_config, &lp5_spd_info, half_populated, &dimms_changed); } diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c index 837a528..9728a99 100644 --- a/src/mainboard/prodrive/atlas/romstage_fsp_params.c +++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c @@ -32,6 +32,7 @@ FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; const struct mb_cfg *mem_config = &ddr5_mem_config; const bool half_populated = false; + bool dimms_changed = false; const struct mem_spd dimm_module_spd_info = { .topo = MEM_TOPO_DIMM_MODULE, @@ -47,5 +48,5 @@ }, }; - memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated); + memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated, &dimms_changed); } diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index debdef2..98482e3 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -110,6 +110,6 @@ }; void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, - const struct mem_spd *spd_info, bool half_populated); + const struct mem_spd *spd_info, bool half_populated, bool *dimms_changed); #endif /* _SOC_ALDERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 9c1f667..8b54cb1 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -236,7 +236,7 @@ } void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, - const struct mem_spd *spd_info, bool half_populated) + const struct mem_spd *spd_info, bool half_populated, bool *dimms_changed) { struct mem_channel_data data; bool dq_dqs_auto_detect = false; @@ -278,7 +278,8 @@ die("Unsupported memory type(%d)\n", mb_cfg->type); } - mem_populate_channel_data(&soc_mem_cfg[mb_cfg->type], spd_info, half_populated, &data); + mem_populate_channel_data(&soc_mem_cfg[mb_cfg->type], spd_info, half_populated, &data, + dimms_changed); mem_init_spd_upds(mem_cfg, &data); mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); diff --git a/src/soc/intel/common/block/include/intelblocks/meminit.h b/src/soc/intel/common/block/include/intelblocks/meminit.h index 1fed02f..130249c 100644 --- a/src/soc/intel/common/block/include/intelblocks/meminit.h +++ b/src/soc/intel/common/block/include/intelblocks/meminit.h @@ -134,11 +134,13 @@ * the mainboard. * spd_info : Information about the memory topology. * half_populated: Hint from mainboard if channels are half populated. + * dimms_changed: True if the dimms is changed after caching the spd data. */ void mem_populate_channel_data(const struct soc_mem_cfg *soc_mem_cfg, const struct mem_spd *spd_info, bool half_populated, - struct mem_channel_data *data); + struct mem_channel_data *data, + bool *dimms_changed); /* * Given a channel number and the maximum number of supported channels, this diff --git a/src/soc/intel/common/block/memory/Kconfig b/src/soc/intel/common/block/memory/Kconfig index fdcccbf..7156be7 100644 --- a/src/soc/intel/common/block/memory/Kconfig +++ b/src/soc/intel/common/block/memory/Kconfig @@ -28,4 +28,12 @@ support is expected to set MRC_CHANNEL_WIDTH as per the FSP MRC expectation. +config SPD_CACHE_ENABLE + bool + default n + help + Enable to cache the spd data to the RW_SPD_CACHE region. If + this option is enabled, please make sure the RW_SPD_CACHE + region is added to the flash layout. + endif diff --git a/src/soc/intel/common/block/memory/meminit.c b/src/soc/intel/common/block/memory/meminit.c index 78dc2d4..89cd4e3 100644 --- a/src/soc/intel/common/block/memory/meminit.c +++ b/src/soc/intel/common/block/memory/meminit.c @@ -5,6 +5,7 @@ #include <intelblocks/meminit.h> #include <commonlib/region.h> #include <spd_bin.h> +#include <spd_cache.h> #include <string.h> #include <types.h> @@ -96,7 +97,7 @@ static bool read_spd_dimm(const struct soc_mem_cfg *soc_mem_cfg, const struct mem_spd *info, bool half_populated, struct mem_channel_data *channel_data, - size_t *spd_len) + size_t *spd_len, bool *dimms_changed) { size_t ch, dimm; struct spd_block blk = { 0 }; @@ -108,6 +109,7 @@ * channel is marked as populated. */ uint32_t pop_mask = 0; + *dimms_changed = false; if (!(info->topo & MEM_TOPO_DIMM_MODULE)) return false; @@ -119,7 +121,46 @@ } } - get_spd_smbus(&blk); + if (CONFIG(SPD_CACHE_ENABLE)) { + uint8_t *spd_cache; + size_t spd_cache_sz; + bool need_update_cache = false; + bool dimm_changed = true; + + /* load spd cache from RW_SPD_CACHE */ + if (load_spd_cache(&spd_cache, &spd_cache_sz) == CB_SUCCESS) { + if (!spd_cache_is_valid(spd_cache, spd_cache_sz)) { + printk(BIOS_WARNING, "Invalid SPD cache\n"); + } else { + dimm_changed = check_if_dimm_changed(spd_cache, &blk); + if (dimm_changed) { + /* + * Set flag to indicate that the + * mrc_cache need to be invalidated + */ + printk(BIOS_INFO, + "DIMM change, invalidate cache.\n"); + *dimms_changed = true; + } + } + need_update_cache = true; + } + + if (!dimm_changed) { + printk(BIOS_INFO, "Use the SPD cache data\n"); + spd_fill_from_cache(spd_cache, &blk); + } else { + /* Access memory info through SMBUS. */ + get_spd_smbus(&blk); + + if (need_update_cache && + update_spd_cache(&blk) == CB_ERR) + printk(BIOS_ERR, "update SPD cache failed\n"); + } + } else { + get_spd_smbus(&blk); + } + *spd_len = blk.len; for (ch = 0; ch < num_phys_ch; ch++) { @@ -145,7 +186,8 @@ void mem_populate_channel_data(const struct soc_mem_cfg *soc_mem_cfg, const struct mem_spd *spd_info, bool half_populated, - struct mem_channel_data *data) + struct mem_channel_data *data, + bool *dimms_changed) { size_t spd_md_len = 0, spd_dimm_len = 0; bool have_dimms; @@ -153,7 +195,8 @@ memset(data, 0, sizeof(*data)); read_spd_md(soc_mem_cfg, spd_info, half_populated, data, &spd_md_len); - have_dimms = read_spd_dimm(soc_mem_cfg, spd_info, half_populated, data, &spd_dimm_len); + have_dimms = read_spd_dimm(soc_mem_cfg, spd_info, half_populated, data, + &spd_dimm_len, dimms_changed); if (data->ch_population_flags == NO_CHANNEL_POPULATED) die("No channels are populated. Incorrect memory configuration!\n"); diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index ce6316e..e8c7b68 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -151,11 +151,13 @@ const struct mem_spd *spd_info, bool half_populated) { struct mem_channel_data data; + bool dimms_changed = false; if (mb_cfg->type >= ARRAY_SIZE(soc_mem_cfg)) die("Invalid memory type(%x)!\n", mb_cfg->type); - mem_populate_channel_data(&soc_mem_cfg[mb_cfg->type], spd_info, half_populated, &data); + mem_populate_channel_data(&soc_mem_cfg[mb_cfg->type], spd_info, half_populated, &data, + &dimms_changed); mem_init_spd_upds(mem_cfg, &data); mem_init_dq_upds(mem_cfg, &data, mb_cfg); mem_init_dqs_upds(mem_cfg, &data, mb_cfg); -- To view, visit https://review.coreboot.org/c/coreboot/+/62294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Gerrit-Change-Number: 62294 Gerrit-PatchSet: 6 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: util/docker/coreboot-jenkins-node: Alphabetize installed tools
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62446 ) Change subject: util/docker/coreboot-jenkins-node: Alphabetize installed tools ...................................................................... util/docker/coreboot-jenkins-node: Alphabetize installed tools It's easier to read and to add new packages when each package is on its own line and they're sorted alphabetically. Indenting them also makes it easier to see what's getting installed and what's a command. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ibfe297bd408ed0783fcff09c1ecb5672fe785c48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62446 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/docker/coreboot-jenkins-node/Dockerfile 1 file changed, 21 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index 2926163..526487e 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -25,12 +25,16 @@ RUN apt-get -y update && \ apt-get -y install \ - parallel \ - meson ninja-build \ - sdcc \ - linkchecker \ - lua5.3 liblua5.3-dev default-jre-headless openssh-server && \ - apt-get clean + default-jre-headless \ + liblua5.3-dev \ + linkchecker \ + lua5.3 \ + meson \ + ninja-build \ + openssh-server \ + parallel \ + sdcc \ + && apt-get clean # Because of the way that the variables are being replaced, docker's 'COPY' # command does not work @@ -63,10 +67,17 @@ COPY --from=zephyr-sdk /opt/zephyr-sdk /opt/zephyr-sdk RUN apt-get update && \ - apt-get install -y python3-pip pykwalify python3-yaml \ - python3-pyelftools python3-jsonschema python3-colorama \ - python3-pyrsistent python3-setuptools swig && \ - apt-get clean + apt-get install -y \ + python3-pip \ + pykwalify \ + python3-yaml \ + python3-pyelftools \ + python3-jsonschema \ + python3-colorama \ + python3-pyrsistent \ + python3-setuptools \ + swig \ + && apt-get clean RUN mkdir /tmp/b && cd /tmp/b && \ git clone https://git.kernel.org/pub/scm/utils/dtc/dtc.git dtc && \ -- To view, visit https://review.coreboot.org/c/coreboot/+/62446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfe297bd408ed0783fcff09c1ecb5672fe785c48 Gerrit-Change-Number: 62446 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/docker/coreboot-jenkins-node: add linkchecker
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62445 ) Change subject: util/docker/coreboot-jenkins-node: add linkchecker ...................................................................... util/docker/coreboot-jenkins-node: add linkchecker The linkchecker tool is now being used to find broken links in our websites. Since it's not needed for building anything, just add it to the jenkins-node Dockerfile instead. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Iac2246b5378e556b5cd9f2107fc5a7e51d583b5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62445 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/docker/coreboot-jenkins-node/Dockerfile 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index 19670b4..2926163 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -28,6 +28,7 @@ parallel \ meson ninja-build \ sdcc \ + linkchecker \ lua5.3 liblua5.3-dev default-jre-headless openssh-server && \ apt-get clean -- To view, visit https://review.coreboot.org/c/coreboot/+/62445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac2246b5378e556b5cd9f2107fc5a7e51d583b5b Gerrit-Change-Number: 62445 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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