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Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62466 )
Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
......................................................................
Patch Set 3:
(5 comments)
Patchset:
PS3:
> @Sumeet, in variant_update_power_limits not change the soc_config value, only update the dpft settin […]
I feel it's fine.
File src/mainboard/google/brya/variants/kano/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62466/comment/ac3a009e_0c141ab5
PS3, Line 134: 20000
Lowering PL1 max power value will impact the overall system performance.
https://review.coreboot.org/c/coreboot/+/62466/comment/03d6aeb9_06c96221
PS3, Line 141: 43000
Normally, we keep max and min power value the same for PL2. So, I would suggest if you are changing PL2 max from 40000mW to 43000mW, change PL2 min as well to 43000mW.
File src/mainboard/google/brya/variants/kano/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62466/comment/1f4defef_578d6ae7
PS3, Line 10: 43000
Normally, we keep max and min value the same for PL2. So, I would suggest if you are changing PL2 max from 40000mW to 43000mW, change PL2 min as well to 43000mW.
https://review.coreboot.org/c/coreboot/+/62466/comment/95d8b4a9_89871f7f
PS3, Line 10: 20000
Do you mean these new values are suggested by your thermal team for this platform ?
Is that the reason these values are changed here ?
Can you please add me in this bug, I can't access it. I would like to understand the reason behind this change. Thanks.
If you are lowering the PL1 max value from 28000mW to 20000mW, it will impact the overall system performance.
Did you test with any performance benchmarks with this new value ? Did you check any impact ?
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Change subject: mb/google/brask/variants/moli: Reduce PSysMax to 11 A
......................................................................
Patch Set 9: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62374/comment/5f867fd8_bc252c29
PS2, Line 9: set psys_imax_ma to 11000 mA for moli
> Maybe: […]
I'm pretty sure this is the rating of the power supply (AC adapter)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62374/comment/bed4a196_92212336
PS9, Line 9: 214.5W
Wow, that's a lot of power.
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Change subject: ec/starlabs/merlin: Don't report a battery capacity higher than design capacity
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Out of curiosity, where does the value for B1FC come from? I guess it comes from the EC, which eithe […]
Yup, from the EC via battery controller.
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Change subject: ec/starlabs/merlin: Don't report a battery capacity higher than design capacity
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
Out of curiosity, where does the value for B1FC come from? I guess it comes from the EC, which either calculates the value or gets it from a smart battery controller.
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Change subject: mb/google/brya/var/nivviks: Correct GPIO S7 config
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62513/comment/f0192db9_1d7aac85
PS1, Line 10: configured to GPP_S6
> 1. Please add a dot/period at the end of sentences. […]
GPP_S6 was configured twice instead of GPP_S7. Hence corrected it to configure GPP_S7 as per the schematics.
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Hello build bot (Jenkins), Kangheui Won, Rizwan Qureshi, Reka Norman, Tim Wawrzynczak, Krishna P Bhat D,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/brya/var/nivviks: Correct GPIO S7 config
......................................................................
mb/google/brya/var/nivviks: Correct GPIO S7 config
Update nivviks gpio file to configure GPP_S7 as per schematics which is
currently configured to GPP_S6.
Signed-off-by: Usha P <usha.p(a)intel.com>
Change-Id: I67f3d3df06916f8163ff4a66f1f681d1eba27137
---
M src/mainboard/google/brya/variants/nivviks/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/62513/2
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Change subject: mb/google/brya/var/nivviks: Correct GPIO S7 config
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62513/comment/bdb0d5b2_ea475ac6
PS1, Line 10: configured to GPP_S6
1. Please add a dot/period at the end of sentences.
2. Please mention the source – probably schematics. (Were they updated?)
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Change subject: mb/google/brya/var/nivviks: Configure WCAM DMIC data pin
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62511/comment/692f9c14_c199c911
PS2, Line 9: GPP_S6 was accidentally configured twice instead of configuring GPP_S7.
… according to schematics.
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Change subject: soc/intel/denverton_ns/cpu: Get CPU frequencies for SMBIOS type 4
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Patch Set 2: Code-Review+1
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Change subject: ec/starlabs/merlin: Don't report a battery capacity higher than design capacity
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Patch Set 2: Code-Review+1
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