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Change subject: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
Hi all, would you please help submit this change? Thanks a lot.
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Change subject: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62465/comment/db3878cf_1fa4a91e
PS4, Line 9: With GPP_B3 locked, primus eMMC SKU encounter eMMC storage
: lost after warm reboot.
: Config GPP_B3 unlocked to make reboot works on primus.
> Please reflow for 72 characters per line, and either add exactly one blank line between paragraphs, […]
Done
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Hello build bot (Jenkins), Subrata Banik, Terry Chen, Malik Hsu, Tim Wawrzynczak, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62465
to look at the new patch set (#6).
Change subject: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
......................................................................
mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after
warm reboot.
Config GPP_B3 unlocked to make reboot works on primus. Also set
GPP_B3 to low in early_gpio_table to meet eMMC-PCIe bridge IC power
on sequence.
BUG=b:221488504
TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage
test reboot 30 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com>
Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6
---
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus4es/gpio.c
2 files changed, 6 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/62465/6
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Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62472 )
Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
@yu-ping,
any suggestion for this patch?
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Change subject: mb/google/nissa: Add fmd file for nissa
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS4:
> Uploaded https://crrev.com/i/4584911 […]
Done. Thanks!
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Hello build bot (Jenkins), Subrata Banik, Kangheui Won, Reka Norman, Tim Wawrzynczak, Rizwan Qureshi,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: mb/google/nissa: Add fmd file for nissa
......................................................................
mb/google/nissa: Add fmd file for nissa
Nissa boards are curretly using chromeos.fmd file of brya. The SPI flash
layout for brya is of 32MB size, and nissa is expected to have 16MB SPI
NOR flash. The current composition of AP firmware exceeds 16MB. To get
an estimate of the unutilized region in the current flash layout for
nissa, added RW_UNUSED regions. The idea is to reduce the AP firmware
size to under 16MB and to remove the RW_UNUSED regions from the final
fmd file.
Below table gives the size reduction from brya fmd to nissa fmd:
+----------------+-------------------+---------------+
| Region | Earlier size (KB) | New size (KB) |
+================+===================+===============+
| SI_ME | 5116 | 3772 |
+----------------+-------------------+---------------+
| RW_SECTION_A/B | 8192 | 4344 |
+----------------+-------------------+---------------+
| VBLOCK_A/B | 64 | 8 |
+----------------+-------------------+---------------+
| ME_RW_A/B* | 3008 | 1434 |
+----------------+-------------------+---------------+
| RW_LEGACY | 2048 | 1024 |
+----------------+-------------------+---------------+
| RW_ELOG | 16 | 4 |
+----------------+-------------------+---------------+
| SHARED_DATA | 8 | 4 |
+----------------+-------------------+---------------+
| VBLOCK_DEV | 8 | 0 |
+----------------+-------------------+---------------+
| RW_SPD_CACHE | 4 | 0 |
+----------------+-------------------+---------------+
| RW_NVRAM | 24 | 8 |
+----------------+-------------------+---------------+
| WP_RO | 8192 | 4096 |
+----------------+-------------------+---------------+
| GBB | 448 | 12 |
+----------------+-------------------+---------------+
*Based on LZMA compression on ME_RW_A/B regions. With LZMA compression,
this region can be 1434K. Without this, ~665K will be more in each of
these regions.
Patch: https://review.coreboot.org/c/coreboot/+/62358/
BUG=b:202783191
BRANCH=None
TEST=Build and boot Nivviks.
Cq-Depend: chrome-internal:4584911
Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
---
M src/mainboard/google/brya/Kconfig
A src/mainboard/google/brya/chromeos-nissa.fmd
2 files changed, 59 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62372/5
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Change subject: mb/google/dedede/var/madoo: Remove Hynix memory for madoo
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Trying to clarify the reason behind this in https://buganizer.corp.google.com/issues/209889645#comment15
Thanks!
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Change subject: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62355/comment/23047253_d75242cd
PS2, Line 24: and call that from smm_module_handler.
Maybe a nicer way would be to define an smm_get_cbmemc_buffer(void *buffer_out, size_t *size_out) function that the cbmemc_init() can call?
File src/cpu/x86/smm/smm_module_handler.c:
https://review.coreboot.org/c/coreboot/+/62355/comment/0a5e17fb_0b5d224b
PS2, Line 17: size_t cbmemc_size;
Since these are global symbols, please namespace them a bit better (e.g. smm_cbmemc_buffer/smm_cbmemc_size or something like that).
File src/lib/cbmem_console.c:
https://review.coreboot.org/c/coreboot/+/62355/comment/0e28d461_e1e46b7a
PS2, Line 90: extern size_t cbmemc_size;
These should probably go in some SMM-specific header and then be included here.
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62192 )
Change subject: soc/intel/common: Retry END_OF_POST command
......................................................................
Patch Set 6:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62192/comment/c5fd7e07_8e4c5fee
PS6, Line 11: max 3 times before triggering the error handling flow.
> What is the problem, and why is the retry needed? Why three and not less or more?
Since EOP command is critical to maintain platform security, so retries are recommended by Intel CSE BIOS Spec for certain scenarios (no response message within 5 seconds or received garbled message).
Patchset:
PS6:
> Are new debug messages printed?
Sorry, I didn't get. I didn't add any debug messages in this patch.
File src/soc/intel/common/block/cse/cse_eop.c:
https://review.coreboot.org/c/coreboot/+/62192/comment/fcb72b95_fd159113
PS6, Line 55: case CSE_TX_ERR_CSE_NOT_READY:
> Does this need fallthrough statements? Does clang build the image without problems?
Yes, I didn't notice any issues.
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