coreboot-gerrit March 2022

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Change in coreboot[master]: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code
by Subrata Banik (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, Zhuohao Lee. Hello Tim Wawrzynczak, Nick Vaccaro, Eric Lai, Patrick Rudolph, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62738 to look at the new patch set (#4). Change subject: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code ...................................................................... {mb, soc}: Move mrc_cache invalidating logic into `memory` common code Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 --- M src/mainboard/google/brya/romstage.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/shadowmountain/romstage.c M src/mainboard/prodrive/atlas/romstage_fsp_params.c M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c M src/soc/intel/common/block/include/intelblocks/meminit.h M src/soc/intel/common/block/memory/meminit.c M src/soc/intel/tigerlake/meminit.c 9 files changed, 19 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/62738/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Gerrit-Change-Number: 62738 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code
by Subrata Banik (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, Zhuohao Lee. Hello Tim Wawrzynczak, Nick Vaccaro, Eric Lai, Patrick Rudolph, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62738 to look at the new patch set (#3). Change subject: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code ...................................................................... {mb, soc}: Move mrc_cache invalidating logic into `memory` common code Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 --- M src/mainboard/google/brya/romstage.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/shadowmountain/romstage.c M src/mainboard/prodrive/atlas/romstage_fsp_params.c M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c M src/soc/intel/common/block/include/intelblocks/meminit.h M src/soc/intel/common/block/memory/meminit.c M src/soc/intel/tigerlake/meminit.c 9 files changed, 18 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/62738/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Gerrit-Change-Number: 62738 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code
by Subrata Banik (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, Zhuohao Lee. Hello Tim Wawrzynczak, Nick Vaccaro, Eric Lai, Patrick Rudolph, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62738 to look at the new patch set (#2). Change subject: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code ...................................................................... {mb, soc}: Move mrc_cache invalidating logic into `memory` common code Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 --- M src/mainboard/google/brya/romstage.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/shadowmountain/romstage.c M src/mainboard/prodrive/atlas/romstage_fsp_params.c M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c M src/soc/intel/common/block/include/intelblocks/meminit.h M src/soc/intel/common/block/memory/meminit.c M src/soc/intel/tigerlake/meminit.c 9 files changed, 17 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/62738/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Gerrit-Change-Number: 62738 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype
by Subrata Banik (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Tim Crawford, Sean Rhodes, Subrata Banik, Jeremy Soller, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, Zhuohao Lee. Hello Tim Crawford, Sean Rhodes, Jeremy Soller, Tim Wawrzynczak, Nick Vaccaro, Nick Vaccaro, Eric Lai, Patrick Rudolph, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62736 to look at the new patch set (#2). Change subject: {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype ...................................................................... {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 --- M src/mainboard/google/brya/romstage.c M src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/memory.c M src/mainboard/google/volteer/romstage.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/shadowmountain/romstage.c M src/mainboard/intel/tglrvp/romstage_fsp_params.c M src/mainboard/prodrive/atlas/romstage_fsp_params.c M src/mainboard/starlabs/labtop/variants/tgl/romstage.c M src/mainboard/system76/darp7/romstage.c M src/mainboard/system76/galp5/romstage.c M src/mainboard/system76/gaze16/romstage.c M src/mainboard/system76/lemp10/romstage.c M src/mainboard/system76/oryp8/romstage.c M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 20 files changed, 25 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/62736/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Gerrit-Change-Number: 62736 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code
by Eric Lai (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, Zhuohao Lee. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62738 ) Change subject: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Nice 👍 -- To view, visit https://review.coreboot.org/c/coreboot/+/62738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Gerrit-Change-Number: 62738 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 13:28:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Pass `FSPM_UPD *` argument for spd functions
by Eric Lai (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, Zhuohao Lee. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62737 ) Change subject: soc/intel/common: Pass `FSPM_UPD *` argument for spd functions ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I770cfd05194c33e11f98f95c5b93157b0ead70c1 Gerrit-Change-Number: 62737 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 13:27:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype
by Eric Lai (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Tim Crawford, Sean Rhodes, Subrata Banik, Jeremy Soller, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, Zhuohao Lee. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62736 ) Change subject: {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Gerrit-Change-Number: 62736 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 13:26:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code
by build bot (Jenkins) (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62738 ) Change subject: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/memory/meminit.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143726): https://review.coreboot.org/c/coreboot/+/62738/comment/c6e90dbb_1280d155 PS1, Line 143: memupd->FspmArchUpd.BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/62738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Gerrit-Change-Number: 62738 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 13:17:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code
by Subrata Banik (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62738 ) Change subject: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code ...................................................................... {mb, soc}: Move mrc_cache invalidating logic into `memory` common code Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 --- M src/mainboard/google/brya/romstage.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/shadowmountain/romstage.c M src/mainboard/prodrive/atlas/romstage_fsp_params.c M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c M src/soc/intel/common/block/include/intelblocks/meminit.h M src/soc/intel/common/block/memory/meminit.c M src/soc/intel/tigerlake/meminit.c 9 files changed, 18 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/62738/1 diff --git a/src/mainboard/google/brya/romstage.c b/src/mainboard/google/brya/romstage.c index 2560840..4e88eca 100644 --- a/src/mainboard/google/brya/romstage.c +++ b/src/mainboard/google/brya/romstage.c @@ -12,7 +12,6 @@ const struct mb_cfg *mem_config = variant_memory_params(); bool half_populated = variant_is_half_populated(); struct mem_spd spd_info; - bool dimms_changed = false; memset(&spd_info, 0, sizeof(spd_info)); variant_get_spd_info(&spd_info); @@ -20,11 +19,7 @@ const struct pad_config *pads; size_t pads_num; - memcfg_init(memupd, mem_config, &spd_info, half_populated, &dimms_changed); - if (dimms_changed) { - memupd->FspmArchUpd.NvsBufferPtr = 0; - memupd->FspmArchUpd.BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; - } + memcfg_init(memupd, mem_config, &spd_info, half_populated); pads = variant_romstage_gpio_table(&pads_num); gpio_configure_pads(pads, pads_num); diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 8a24529..e29b7d4 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -48,7 +48,6 @@ const struct mb_cfg *mem_config = variant_memory_params(); int board_id = get_board_id(); const bool half_populated = false; - bool dimms_changed = false; const struct mem_spd memory_down_spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, @@ -73,8 +72,7 @@ case ADL_P_DDR4_1: case ADL_P_DDR4_2: case ADL_P_DDR5_1: - memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated, - &dimms_changed); + memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated); break; case ADL_P_DDR5_2: case ADL_P_LP4_1: @@ -84,8 +82,7 @@ case ADL_M_LP4: case ADL_M_LP5: case ADL_N_LP5: - memcfg_init(memupd, mem_config, &memory_down_spd_info, half_populated, - &dimms_changed); + memcfg_init(memupd, mem_config, &memory_down_spd_info, half_populated); break; default: die("Unknown board id = 0x%x\n", board_id); diff --git a/src/mainboard/intel/shadowmountain/romstage.c b/src/mainboard/intel/shadowmountain/romstage.c index 996df2c..49f579b 100644 --- a/src/mainboard/intel/shadowmountain/romstage.c +++ b/src/mainboard/intel/shadowmountain/romstage.c @@ -12,12 +12,11 @@ FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; const struct mb_cfg *mem_config = variant_memory_params(); const bool half_populated = false; - bool dimms_changed = false; const struct mem_spd lp5_spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, .cbfs_index = variant_memory_sku(), }; - memcfg_init(memupd, mem_config, &lp5_spd_info, half_populated, &dimms_changed); + memcfg_init(memupd, mem_config, &lp5_spd_info, half_populated); } diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c index a42a97a..cfd6507 100644 --- a/src/mainboard/prodrive/atlas/romstage_fsp_params.c +++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c @@ -32,7 +32,6 @@ FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; const struct mb_cfg *mem_config = &ddr5_mem_config; const bool half_populated = false; - bool dimms_changed = false; const struct mem_spd dimm_module_spd_info = { .topo = MEM_TOPO_DIMM_MODULE, @@ -48,5 +47,5 @@ }, }; - memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated, &dimms_changed); + memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated); } diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 6af0acc..bd75636 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -110,6 +110,6 @@ }; void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, - const struct mem_spd *spd_info, bool half_populated, bool *dimms_changed); + const struct mem_spd *spd_info, bool half_populated); #endif /* _SOC_ALDERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 2c915ef..d40ee35 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -236,7 +236,7 @@ } void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, - const struct mem_spd *spd_info, bool half_populated, bool *dimms_changed) + const struct mem_spd *spd_info, bool half_populated) { struct mem_channel_data data; bool dq_dqs_auto_detect = false; @@ -280,7 +280,7 @@ } mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated, - &data, dimms_changed); + &data); mem_init_spd_upds(mem_cfg, &data); mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); diff --git a/src/soc/intel/common/block/include/intelblocks/meminit.h b/src/soc/intel/common/block/include/intelblocks/meminit.h index c01daf4..391ab1b 100644 --- a/src/soc/intel/common/block/include/intelblocks/meminit.h +++ b/src/soc/intel/common/block/include/intelblocks/meminit.h @@ -136,13 +136,11 @@ * the mainboard. * spd_info : Information about the memory topology. * half_populated: Hint from mainboard if channels are half populated. - * dimms_changed: True if the dimms is changed after caching the spd data. */ void mem_populate_channel_data(FSPM_UPD *memupd, const struct soc_mem_cfg *soc_mem_cfg, const struct mem_spd *spd_info, bool half_populated, - struct mem_channel_data *data, - bool *dimms_changed); + struct mem_channel_data *data); /* * Given a channel number and the maximum number of supported channels, this diff --git a/src/soc/intel/common/block/memory/meminit.c b/src/soc/intel/common/block/memory/meminit.c index 272e6a1..6b3d4d9 100644 --- a/src/soc/intel/common/block/memory/meminit.c +++ b/src/soc/intel/common/block/memory/meminit.c @@ -98,7 +98,7 @@ static bool read_spd_dimm(FSPM_UPD *memupd, const struct soc_mem_cfg *soc_mem_cfg, const struct mem_spd *info, bool half_populated, struct mem_channel_data *channel_data, - size_t *spd_len, bool *dimms_changed) + size_t *spd_len) { size_t ch, dimm; struct spd_block blk = { 0 }; @@ -110,7 +110,6 @@ * channel is marked as populated. */ uint32_t pop_mask = 0; - *dimms_changed = false; if (!(info->topo & MEM_TOPO_DIMM_MODULE)) return false; @@ -134,14 +133,14 @@ printk(BIOS_WARNING, "Invalid SPD cache\n"); } else { dimm_changed = check_if_dimm_changed(spd_cache, &blk); - if (dimm_changed) { + if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != 0) { /* - * Set flag to indicate that the + * Set FSP-M Arch UPD to indicate that the * mrc_cache need to be invalidated */ - printk(BIOS_INFO, - "DIMM change, invalidate cache.\n"); - *dimms_changed = true; + printk(BIOS_INFO, "DIMM change, invalidate cache.\n"); + memupd->FspmArchUpd.NvsBufferPtr = 0; + memupd->FspmArchUpd.BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; } } need_update_cache = true; @@ -187,8 +186,7 @@ void mem_populate_channel_data(FSPM_UPD *memupd, const struct soc_mem_cfg *soc_mem_cfg, const struct mem_spd *spd_info, bool half_populated, - struct mem_channel_data *data, - bool *dimms_changed) + struct mem_channel_data *data) { size_t spd_md_len = 0, spd_dimm_len = 0; bool have_dimms; @@ -197,7 +195,7 @@ read_spd_md(soc_mem_cfg, spd_info, half_populated, data, &spd_md_len); have_dimms = read_spd_dimm(memupd, soc_mem_cfg, spd_info, half_populated, data, - &spd_dimm_len, dimms_changed); + &spd_dimm_len); if (data->ch_population_flags == NO_CHANNEL_POPULATED) die("No channels are populated. Incorrect memory configuration!\n"); diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 10c57a5..368e071 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -151,14 +151,13 @@ const struct mem_spd *spd_info, bool half_populated) { struct mem_channel_data data; - bool dimms_changed = false; FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; if (mb_cfg->type >= ARRAY_SIZE(soc_mem_cfg)) die("Invalid memory type(%x)!\n", mb_cfg->type); mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated, - &data, &dimms_changed); + &data); mem_init_spd_upds(mem_cfg, &data); mem_init_dq_upds(mem_cfg, &data, mb_cfg); mem_init_dqs_upds(mem_cfg, &data, mb_cfg); -- To view, visit https://review.coreboot.org/c/coreboot/+/62738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Gerrit-Change-Number: 62738 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Pass `FSPM_UPD *` argument for spd functions
by Subrata Banik (Code Review) 10 Mar '22

10 Mar '22

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