coreboot-gerrit March 2022

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Change in coreboot[master]: {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype
by Subrata Banik (Code Review) 10 Mar '22

10 Mar '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62736 ) Change subject: {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype ...................................................................... {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 --- M src/mainboard/google/brya/romstage.c M src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/memory.c M src/mainboard/google/volteer/romstage.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/shadowmountain/romstage.c M src/mainboard/intel/tglrvp/romstage_fsp_params.c M src/mainboard/prodrive/atlas/romstage_fsp_params.c M src/mainboard/starlabs/labtop/variants/tgl/romstage.c M src/mainboard/system76/darp7/romstage.c M src/mainboard/system76/galp5/romstage.c M src/mainboard/system76/gaze16/romstage.c M src/mainboard/system76/lemp10/romstage.c M src/mainboard/system76/oryp8/romstage.c M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 20 files changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/62736/1 diff --git a/src/mainboard/google/brya/romstage.c b/src/mainboard/google/brya/romstage.c index a00cf32..2560840 100644 --- a/src/mainboard/google/brya/romstage.c +++ b/src/mainboard/google/brya/romstage.c @@ -9,7 +9,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; const struct mb_cfg *mem_config = variant_memory_params(); bool half_populated = variant_is_half_populated(); struct mem_spd spd_info; @@ -21,7 +20,7 @@ const struct pad_config *pads; size_t pads_num; - memcfg_init(m_cfg, mem_config, &spd_info, half_populated, &dimms_changed); + memcfg_init(memupd, mem_config, &spd_info, half_populated, &dimms_changed); if (dimms_changed) { memupd->FspmArchUpd.NvsBufferPtr = 0; memupd->FspmArchUpd.BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; diff --git a/src/mainboard/google/deltaur/romstage.c b/src/mainboard/google/deltaur/romstage.c index c04f6fb..f9d71a8 100644 --- a/src/mainboard/google/deltaur/romstage.c +++ b/src/mainboard/google/deltaur/romstage.c @@ -5,6 +5,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { - FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - variant_memory_init(mem_cfg); + variant_memory_init(mupd); } diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h index 7a4ed08..6804ef6 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h @@ -19,7 +19,7 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); const struct mb_cfg *variant_memory_params(void); -void variant_memory_init(FSP_M_CONFIG *mem_cfg); +void variant_memory_init(FSPM_UPD *mupd); /* SKU ID structure */ typedef struct { diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c index caa99a9..37c21cc 100644 --- a/src/mainboard/google/deltaur/variants/deltan/memory.c +++ b/src/mainboard/google/deltaur/variants/deltan/memory.c @@ -61,7 +61,7 @@ .ect = false, /* Disable Early Command Training */ }; -void variant_memory_init(FSP_M_CONFIG *mem_cfg) +void variant_memory_init(FSPM_UPD *mupd) { const struct mem_spd spd_info = { .topo = MEM_TOPO_DIMM_MODULE, @@ -77,5 +77,5 @@ new_board_cfg_ddr4.ddr4_config.dq_pins_interleaved = gpio_get(MEMORY_INTERLEAVED); - memcfg_init(mem_cfg, &new_board_cfg_ddr4, &spd_info, half_populated); + memcfg_init(mupd, &new_board_cfg_ddr4, &spd_info, half_populated); } diff --git a/src/mainboard/google/deltaur/variants/deltaur/memory.c b/src/mainboard/google/deltaur/variants/deltaur/memory.c index f8506df54..a2037a8 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/memory.c +++ b/src/mainboard/google/deltaur/variants/deltaur/memory.c @@ -77,7 +77,7 @@ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); } -void variant_memory_init(FSP_M_CONFIG *mem_cfg) +void variant_memory_init(FSPM_UPD *mupd) { const struct mb_cfg *board_cfg = variant_memory_params(); const struct mem_spd spd_info = { @@ -85,5 +85,5 @@ .cbfs_index = variant_memory_sku(), }; const bool half_populated = false; - memcfg_init(mem_cfg, board_cfg, &spd_info, half_populated); + memcfg_init(mupd, board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 8cde5da..f504039 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -21,7 +21,7 @@ }; bool half_populated = gpio_get(GPIO_MEM_CH_SEL); - memcfg_init(mem_cfg, board_cfg, &spd_info, half_populated); + memcfg_init(mupd, board_cfg, &spd_info, half_populated); memcfg_variant_init(mupd); } diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 5b5cc6b..8a24529 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -73,7 +73,7 @@ case ADL_P_DDR4_1: case ADL_P_DDR4_2: case ADL_P_DDR5_1: - memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated, + memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated, &dimms_changed); break; case ADL_P_DDR5_2: @@ -84,7 +84,7 @@ case ADL_M_LP4: case ADL_M_LP5: case ADL_N_LP5: - memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated, + memcfg_init(memupd, mem_config, &memory_down_spd_info, half_populated, &dimms_changed); break; default: diff --git a/src/mainboard/intel/shadowmountain/romstage.c b/src/mainboard/intel/shadowmountain/romstage.c index 0951936..996df2c 100644 --- a/src/mainboard/intel/shadowmountain/romstage.c +++ b/src/mainboard/intel/shadowmountain/romstage.c @@ -19,5 +19,5 @@ .cbfs_index = variant_memory_sku(), }; - memcfg_init(m_cfg, mem_config, &lp5_spd_info, half_populated, &dimms_changed); + memcfg_init(memupd, mem_config, &lp5_spd_info, half_populated, &dimms_changed); } diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 3341568..7548f51 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -49,6 +49,6 @@ }; bool half_populated = false; - memcfg_init(mem_cfg, mem_config, &spd_info, half_populated); + memcfg_init(mupd, mem_config, &spd_info, half_populated); } diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c index 9728a99..a42a97a 100644 --- a/src/mainboard/prodrive/atlas/romstage_fsp_params.c +++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c @@ -48,5 +48,5 @@ }, }; - memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated, &dimms_changed); + memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated, &dimms_changed); } diff --git a/src/mainboard/starlabs/labtop/variants/tgl/romstage.c b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c index 1d65c61..fed6efc 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/romstage.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c @@ -25,7 +25,7 @@ }, }; - memcfg_init(&mupd->FspmConfig, &mem_config, &ddr4_spd_info, half_populated); + memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated); const uint8_t vtd = get_uint_option("vtd", 1); mupd->FspmConfig.VtdDisable = !vtd; diff --git a/src/mainboard/system76/darp7/romstage.c b/src/mainboard/system76/darp7/romstage.c index a72b647..eb4fd39 100644 --- a/src/mainboard/system76/darp7/romstage.c +++ b/src/mainboard/system76/darp7/romstage.c @@ -18,5 +18,5 @@ }; const bool half_populated = false; - memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated); + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/system76/galp5/romstage.c b/src/mainboard/system76/galp5/romstage.c index a72b647..eb4fd39 100644 --- a/src/mainboard/system76/galp5/romstage.c +++ b/src/mainboard/system76/galp5/romstage.c @@ -18,5 +18,5 @@ }; const bool half_populated = false; - memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated); + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/system76/gaze16/romstage.c b/src/mainboard/system76/gaze16/romstage.c index f46e83c..119c3f5 100644 --- a/src/mainboard/system76/gaze16/romstage.c +++ b/src/mainboard/system76/gaze16/romstage.c @@ -26,5 +26,5 @@ const bool half_populated = false; - memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated); + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/system76/lemp10/romstage.c b/src/mainboard/system76/lemp10/romstage.c index 6a91620..749efe6 100644 --- a/src/mainboard/system76/lemp10/romstage.c +++ b/src/mainboard/system76/lemp10/romstage.c @@ -18,5 +18,5 @@ }; const bool half_populated = false; - memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated); + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/system76/oryp8/romstage.c b/src/mainboard/system76/oryp8/romstage.c index affe636..64cc844 100644 --- a/src/mainboard/system76/oryp8/romstage.c +++ b/src/mainboard/system76/oryp8/romstage.c @@ -26,5 +26,5 @@ // Enable M.2 PCIE 4.0 and PEG1 mupd->FspmConfig.CpuPcieRpEnableMask = 0x3; - memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated); + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 98482e3..6af0acc 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -109,7 +109,7 @@ uint8_t LpDdrDqDqsReTraining; }; -void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated, bool *dimms_changed); #endif /* _SOC_ALDERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 8b54cb1..31b3ae1 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -235,11 +235,12 @@ mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true); } -void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated, bool *dimms_changed) { struct mem_channel_data data; bool dq_dqs_auto_detect = false; + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; mem_cfg->ECT = mb_cfg->ect; mem_cfg->UserBd = mb_cfg->UserBd; diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index 6b3086c..b51c8ea 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -111,7 +111,7 @@ struct mem_ddr4_config ddr4_config; }; -void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated); #endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index e8c7b68..d5ca9a9 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -147,11 +147,12 @@ mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data); } -void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated) { struct mem_channel_data data; bool dimms_changed = false; + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; if (mb_cfg->type >= ARRAY_SIZE(soc_mem_cfg)) die("Invalid memory type(%x)!\n", mb_cfg->type); -- To view, visit https://review.coreboot.org/c/coreboot/+/62736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Gerrit-Change-Number: 62736 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in qc_blobs[master]: sc7180/boot : Update qclib blobs binaries and release notes
by Sudheer Amrabadi (Code Review) 10 Mar '22

10 Mar '22

Sudheer Amrabadi has uploaded this change for review. ( https://review.coreboot.org/c/qc_blobs/+/62734 ) Change subject: sc7180/boot : Update qclib blobs binaries and release notes ...................................................................... sc7180/boot : Update qclib blobs binaries and release notes Change-Id: I1dace0db7fd1dcd2f34302885e3fec40b63b7eaf --- M sc7180/boot/QcLib.elf M sc7180/boot/Release_Notes.txt M sc7180/boot/dcb.bin 3 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/qc_blobs refs/changes/34/62734/1 diff --git a/sc7180/boot/QcLib.elf b/sc7180/boot/QcLib.elf index 571c484..bfa4235 100644 --- a/sc7180/boot/QcLib.elf +++ b/sc7180/boot/QcLib.elf Binary files differ diff --git a/sc7180/boot/Release_Notes.txt b/sc7180/boot/Release_Notes.txt index 3cbda88..536a937 100644 --- a/sc7180/boot/Release_Notes.txt +++ b/sc7180/boot/Release_Notes.txt @@ -1,3 +1,26 @@ +=================== Release 00037 ================================ +This Release Notes file covers these blobs: + * QcLib.elf + * dcb.bin + +Version : 00037 + +Release Date : Mar, 2022 + +Supported Silicon : SC7180 + +No special instructions, requirements or dependencies, files must be +present in this folder to be pulled in during coreboot build + +Changes since last version : + * Rennell LC | Micron 8GB bitflip issue during WMM fix + +Errata : Nothing to report + +Toolchain Version : LLVM 12.0.0 + +ABI Info : see qclib-interface.txt + =================== Release 00035 ================================ This Release Notes file covers these blobs: * QcLib.elf diff --git a/sc7180/boot/dcb.bin b/sc7180/boot/dcb.bin index 05c9a5b..217ded3 100644 --- a/sc7180/boot/dcb.bin +++ b/sc7180/boot/dcb.bin Binary files differ -- To view, visit https://review.coreboot.org/c/qc_blobs/+/62734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: I1dace0db7fd1dcd2f34302885e3fec40b63b7eaf Gerrit-Change-Number: 62734 Gerrit-PatchSet: 1 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/vell: Add 5G WWAN ACPI support for vell
by Shon Wang (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Tim Wawrzynczak, Robert Chen. Shon Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61847 ) Change subject: mb/google/brya/var/vell: Add 5G WWAN ACPI support for vell ...................................................................... Patch Set 18: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be Gerrit-Change-Number: 61847 Gerrit-PatchSet: 18 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 10 Mar 2022 11:36:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Send EOP early in the boot sequence
by Sridhar Siricilla (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62272 ) Change subject: soc/intel/adl: Send EOP early in the boot sequence ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Gerrit-Change-Number: 62272 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 11:34:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support to control coreboot and Intel SoC features
by Subrata Banik (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Nico Huber, Sridhar Siricilla, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 14: (1 comment) File src/soc/intel/common/basecode/debug/debug_feature.c: https://review.coreboot.org/c/coreboot/+/61380/comment/22d7e961_6a825848 PS14, Line 22: pre_mem_debug_init > This is init function of the runtime debug driver. so, I will maintain debug_ as prefix when new helper functions are added to this file. Make sense? Sure, there is no hard bound that we need to maintain `debug_` across but just thought of floating this idea. Example: https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block… -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 14 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 11:32:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support to control CSE firmware update
by Sridhar Siricilla (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62715 ) Change subject: soc/intel/common: Add support to control CSE firmware update ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/62715/comment/26eadb53_a4ad8e0e PS1, Line 12: #include <intelbasecode/debug_feature.h> > order? Will fix it. Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/62715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f234b142191eb83137d5d83f21e890e1cb828ba Gerrit-Change-Number: 62715 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 11:28:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Nico Huber, Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 14: (4 comments) File src/soc/intel/common/basecode/debug/Kconfig: https://review.coreboot.org/c/coreboot/+/61380/comment/8a0bf807_9a50d4d9 PS14, Line 5: Driver to control run time features of Intel SoC & coreboot > can you please give some examples so user know when to select this Kconfig? Sure, I will improve description. File src/soc/intel/common/basecode/debug/debug_feature.c: https://review.coreboot.org/c/coreboot/+/61380/comment/0f7e5157_564d0475 PS14, Line 9: SI_DESC_OEM_SECTION_OFFSET > Would be good if we can have and entry like SI_DEBUG in SI_DESC in flashmap. […] I will investigate and implement in separate patch if required. https://review.coreboot.org/c/coreboot/+/61380/comment/7d00f7ec_71ec5f22 PS14, Line 22: pre_mem_debug_init > can we try to maintain a prefix like other common code like `debug_` ? This is init function of the runtime debug driver. so, I will maintain debug_ as prefix when new helper functions are added to this file. Make sense? File src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h: https://review.coreboot.org/c/coreboot/+/61380/comment/1643ee35_98f7b79c PS14, Line 3: RT > do we need to specify RT? Not required. -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 14 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 11:27:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support to control coreboot and Intel SoC features
by Rizwan Qureshi (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Nico Huber, Sridhar Siricilla, Patrick Rudolph. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 14: Code-Review+2 (1 comment) File src/soc/intel/common/basecode/debug/debug_feature.c: https://review.coreboot.org/c/coreboot/+/61380/comment/64724724_1bff0b7a PS14, Line 9: SI_DESC_OEM_SECTION_OFFSET Would be good if we can have and entry like SI_DEBUG in SI_DESC in flashmap. This would be easy to reference in tools as well which understand the FMAP. but, you can do that as another patch -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 14 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 10:44:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Describe our Coverity Scan integration
by Felix Singer (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Patrick Georgi, Paul Menzel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62666 ) Change subject: Documentation: Describe our Coverity Scan integration ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File Documentation/infrastructure/coverity.md: https://review.coreboot.org/c/coreboot/+/62666/comment/c14dd96f_b4eb4705 PS2, Line 69: * Chromium EC: [Coverity Scan site](https://scan.coverity.com/projects/chromium-ec?tab=overview) ([build job](https://qa.coreboot.org/view/coverity/job/ChromeEC-Coverity/)) I would put the links at the end of the document to make the Markdown version better readable. -- To view, visit https://review.coreboot.org/c/coreboot/+/62666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a2b68a4b4b54c7345280b252d624799316641b1 Gerrit-Change-Number: 62666 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 10:38:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/galtic: update Wifi SAR for for galnat
by Frank Chu (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Paul Menzel. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62704 ) Change subject: mb/google/dedede/var/galtic: update Wifi SAR for for galnat ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62704/comment/f82e5d9d_6781b320 PS3, Line 10: Using > Use Done https://review.coreboot.org/c/coreboot/+/62704/comment/8ff76f77_b215709a PS3, Line 9: Add wifi sar for galnat/galnat360 : Using convertible mode of SKU ID to load wifi table. > Format it as a list? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I868a7416a002732736cabea48ce80548ea75e517 Gerrit-Change-Number: 62704 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 10:24:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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