coreboot-gerrit March 2022

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Change in coreboot[master]: soc/apollolake: Hook up VTD to CMOS
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61679 ) Change subject: soc/apollolake: Hook up VTD to CMOS ...................................................................... soc/apollolake: Hook up VTD to CMOS Hook up vtd_enable to CMOS value of "vtd". Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I16b43f0489f652d650e820c36b2b9bea61cf3c8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61679 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/chip.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1682490..3ee4920 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -23,6 +23,7 @@ #include <intelblocks/gpio.h> #include <intelblocks/itss.h> #include <intelblocks/pmclib.h> +#include <option.h> #include <soc/cpu.h> #include <soc/heci.h> #include <soc/intel/common/vbt.h> @@ -709,7 +710,7 @@ silconfig->VmxEnable = CONFIG(ENABLE_VMX); /* Set VTD feature according to devicetree */ - silconfig->VtdEnable = cfg->enable_vtd; + silconfig->VtdEnable = get_uint_option("vtd", cfg->enable_vtd); silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); -- To view, visit https://review.coreboot.org/c/coreboot/+/61679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16b43f0489f652d650e820c36b2b9bea61cf3c8c Gerrit-Change-Number: 61679 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/starlabs/labtop: Remove unnecessary return value from MWAK
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62635 ) Change subject: mb/starlabs/labtop: Remove unnecessary return value from MWAK ...................................................................... mb/starlabs/labtop: Remove unnecessary return value from MWAK Don't return 0x00 when running MWAK as it is not needed. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ic62eab8ae5319aff37c61fc29d701d9a36ada919 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62635 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/starlabs/labtop/acpi/sleep.asl 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/starlabs/labtop/acpi/sleep.asl b/src/mainboard/starlabs/labtop/acpi/sleep.asl index b4df10a..7ed74e3 100644 --- a/src/mainboard/starlabs/labtop/acpi/sleep.asl +++ b/src/mainboard/starlabs/labtop/acpi/sleep.asl @@ -8,5 +8,4 @@ Method (MWAK, 1, NotSerialized) { RWAK (Arg0) - Return (0x00) } 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic62eab8ae5319aff37c61fc29d701d9a36ada919 Gerrit-Change-Number: 62635 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs/merlin: Use ECWR function
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62637 ) Change subject: ec/starlabs/merlin: Use ECWR function ...................................................................... ec/starlabs/merlin: Use ECWR function Use ECWR function, instead of writing raw values to emem, to avoid a lack of syncronisation as it uses a mutex. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I90cfd3e1752fe25493bd72ea6bcab1fd9318d2e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62637 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/starlabs/merlin/acpi/suspend.asl 1 file changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl index 70a9bda..679281a 100644 --- a/src/ec/starlabs/merlin/acpi/suspend.asl +++ b/src/ec/starlabs/merlin/acpi/suspend.asl @@ -89,15 +89,15 @@ // 0x01 == Disabled == 0x22 Case (0x00) { - \_SB.PCI0.LPCB.EC.TPLE = 0x00 + \_SB.PCI0.LPCB.EC.ECWR (0x00, RefOf(\_SB.PCI0.LPCB.EC.TPLE)) } Case (0x01) { - \_SB.PCI0.LPCB.EC.TPLE = 0x22 + \_SB.PCI0.LPCB.EC.ECWR (0x22, RefOf(\_SB.PCI0.LPCB.EC.TPLE)) } } - \_SB.PCI0.LPCB.EC.FLKE = \_SB.PCI0.LPCB.FLKC + \_SB.PCI0.LPCB.EC.ECWR (\_SB.PCI0.LPCB.FLKC, RefOf(\_SB.PCI0.LPCB.EC.FLKE)) Switch (ToInteger (\_SB.PCI0.LPCB.KLSC)) { @@ -105,11 +105,11 @@ // 0x01 == Enabled == 0xdd Case (0x00) { - \_SB.PCI0.LPCB.EC.KLSE = 0x00 + \_SB.PCI0.LPCB.EC.ECWR (0x00, RefOf(\_SB.PCI0.LPCB.EC.KLSE)) } Case (0x01) { - \_SB.PCI0.LPCB.EC.KLSE = 0xdd + \_SB.PCI0.LPCB.EC.ECWR (0xdd, RefOf(\_SB.PCI0.LPCB.EC.KLSE)) } } @@ -121,19 +121,19 @@ // 0x03 == High == 0xaa Case (0x00) { - \_SB.PCI0.LPCB.EC.KLBE = 0xdd + \_SB.PCI0.LPCB.EC.ECWR (0xdd, RefOf(\_SB.PCI0.LPCB.EC.KLBE)) } Case (0x01) { - \_SB.PCI0.LPCB.EC.KLBE = 0xcc + \_SB.PCI0.LPCB.EC.ECWR (0xcc, RefOf(\_SB.PCI0.LPCB.EC.KLBE)) } Case (0x02) { - \_SB.PCI0.LPCB.EC.KLBE = 0xbb + \_SB.PCI0.LPCB.EC.ECWR (0xbb, RefOf(\_SB.PCI0.LPCB.EC.KLBE)) } Case (0x03) { - \_SB.PCI0.LPCB.EC.KLBE = 0xaa + \_SB.PCI0.LPCB.EC.ECWR (0xaa, RefOf(\_SB.PCI0.LPCB.EC.KLBE)) } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/62637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90cfd3e1752fe25493bd72ea6bcab1fd9318d2e3 Gerrit-Change-Number: 62637 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs: Write the correct value for KLBE when suspending
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62609 ) Change subject: ec/starlabs: Write the correct value for KLBE when suspending ...................................................................... ec/starlabs: Write the correct value for KLBE when suspending The current code will write the raw value from the CMOS, which doesn't match the respective setting in EC. Switch argument will write the correct value, and prevent the setting being reset. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I40dc78c743f4201a11ea0c26a8af716cab42b805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62609 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/starlabs/merlin/acpi/suspend.asl 1 file changed, 23 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl index c65ca6d..70a9bda 100644 --- a/src/ec/starlabs/merlin/acpi/suspend.asl +++ b/src/ec/starlabs/merlin/acpi/suspend.asl @@ -113,5 +113,27 @@ } } - \_SB.PCI0.LPCB.EC.KLBE = \_SB.PCI0.LPCB.KLBC + Switch (ToInteger (\_SB.PCI0.LPCB.KLBC)) + { + // 0x00 == On == 0xdd + // 0x01 == Off == 0xcc + // 0x02 == Low == 0xbb + // 0x03 == High == 0xaa + Case (0x00) + { + \_SB.PCI0.LPCB.EC.KLBE = 0xdd + } + Case (0x01) + { + \_SB.PCI0.LPCB.EC.KLBE = 0xcc + } + Case (0x02) + { + \_SB.PCI0.LPCB.EC.KLBE = 0xbb + } + Case (0x03) + { + \_SB.PCI0.LPCB.EC.KLBE = 0xaa + } + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/62609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40dc78c743f4201a11ea0c26a8af716cab42b805 Gerrit-Change-Number: 62609 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs: Write the correct value for KLSE when suspending
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62608 ) Change subject: ec/starlabs: Write the correct value for KLSE when suspending ...................................................................... ec/starlabs: Write the correct value for KLSE when suspending The current code will write the raw value from the CMOS, which doesn't match the respective setting in EC. Switch argument will write the correct value, and prevent the setting being reset. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I93444cdb96eaf729630b48551d0853511b584634 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62608 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/starlabs/merlin/acpi/suspend.asl 1 file changed, 15 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl index 0f1c27c..c65ca6d 100644 --- a/src/ec/starlabs/merlin/acpi/suspend.asl +++ b/src/ec/starlabs/merlin/acpi/suspend.asl @@ -98,6 +98,20 @@ } \_SB.PCI0.LPCB.EC.FLKE = \_SB.PCI0.LPCB.FLKC - \_SB.PCI0.LPCB.EC.KLSE = \_SB.PCI0.LPCB.KLSC + + Switch (ToInteger (\_SB.PCI0.LPCB.KLSC)) + { + // 0x00 == Disabled == 0x00 + // 0x01 == Enabled == 0xdd + Case (0x00) + { + \_SB.PCI0.LPCB.EC.KLSE = 0x00 + } + Case (0x01) + { + \_SB.PCI0.LPCB.EC.KLSE = 0xdd + } + } + \_SB.PCI0.LPCB.EC.KLBE = \_SB.PCI0.LPCB.KLBC } -- To view, visit https://review.coreboot.org/c/coreboot/+/62608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93444cdb96eaf729630b48551d0853511b584634 Gerrit-Change-Number: 62608 Gerrit-PatchSet: 13 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs: Write the correct value for TPLE when suspending
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62607 ) Change subject: ec/starlabs: Write the correct value for TPLE when suspending ...................................................................... ec/starlabs: Write the correct value for TPLE when suspending The current code will write the raw value from the CMOS, which doesn't match the respective setting in EC. Switch argument will write the correct value, and prevent the setting being reset. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Iabeec47bf492b698f95d86aa2d08ba9caedd75f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62607 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/starlabs/merlin/acpi/suspend.asl 1 file changed, 15 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl index 81ae8d1..0f1c27c 100644 --- a/src/ec/starlabs/merlin/acpi/suspend.asl +++ b/src/ec/starlabs/merlin/acpi/suspend.asl @@ -82,7 +82,21 @@ \_SB.PCI0.LPCB.EC.OSFG = 0x01 /* Restore EC settings from CMOS */ - \_SB.PCI0.LPCB.EC.TPLE = \_SB.PCI0.LPCB.TPLC + Switch (ToInteger (\_SB.PCI0.LPCB.TPLC)) + { + // 0x00 == Enabled == 0x00 + // 0x00 == Re-enabled == 0x11 + // 0x01 == Disabled == 0x22 + Case (0x00) + { + \_SB.PCI0.LPCB.EC.TPLE = 0x00 + } + Case (0x01) + { + \_SB.PCI0.LPCB.EC.TPLE = 0x22 + } + } + \_SB.PCI0.LPCB.EC.FLKE = \_SB.PCI0.LPCB.FLKC \_SB.PCI0.LPCB.EC.KLSE = \_SB.PCI0.LPCB.KLSC \_SB.PCI0.LPCB.EC.KLBE = \_SB.PCI0.LPCB.KLBC -- To view, visit https://review.coreboot.org/c/coreboot/+/62607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabeec47bf492b698f95d86aa2d08ba9caedd75f6 Gerrit-Change-Number: 62607 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs: Store the correct value for KLBE when suspending
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62606 ) Change subject: ec/starlabs: Store the correct value for KLBE when suspending ...................................................................... ec/starlabs: Store the correct value for KLBE when suspending The current code will read the raw value from the EC, which doesn't match the respective setting in CMOS. Switch argument will store the correct value. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ic2a83df9a270de6d7bab295e732a6c13accbe17c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62606 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/starlabs/merlin/acpi/suspend.asl 1 file changed, 23 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl index a753ba6..81ae8d1 100644 --- a/src/ec/starlabs/merlin/acpi/suspend.asl +++ b/src/ec/starlabs/merlin/acpi/suspend.asl @@ -41,8 +41,29 @@ } } - \_SB.PCI0.LPCB.KLBC = - \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLBE)) + Switch (ToInteger (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLBE)))) + { + // 0xdd == On == 0x00 + // 0xcc == Off == 0x01 + // 0xbb == Low == 0x02 + // 0xaa == High == 0x03 + Case (0xdd) + { + \_SB.PCI0.LPCB.KLBC = 0x00 + } + Case (0xcc) + { + \_SB.PCI0.LPCB.KLBC = 0x01 + } + Case (0xbb) + { + \_SB.PCI0.LPCB.KLBC = 0x02 + } + Case (0xaa) + { + \_SB.PCI0.LPCB.KLBC = 0x03 + } + } } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/62606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2a83df9a270de6d7bab295e732a6c13accbe17c Gerrit-Change-Number: 62606 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs: Store the correct value for KLSE when suspending
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62605 ) Change subject: ec/starlabs: Store the correct value for KLSE when suspending ...................................................................... ec/starlabs: Store the correct value for KLSE when suspending The current code will read the raw value from the EC, which doesn't match the respective setting in CMOS. Switch argument will store the correct value. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I62e0fc3b6fcae72f2d8eacf37a390b4e4b1f0783 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62605 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/starlabs/merlin/acpi/suspend.asl 1 file changed, 15 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl index 9f88a05..a753ba6 100644 --- a/src/ec/starlabs/merlin/acpi/suspend.asl +++ b/src/ec/starlabs/merlin/acpi/suspend.asl @@ -26,8 +26,21 @@ \_SB.PCI0.LPCB.FLKC = \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.FLKE)) - \_SB.PCI0.LPCB.KLSC = - \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLSE)) + + Switch (ToInteger (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLSE)))) + { + // 0x00 == Disabled == 0x00 + // 0xdd == Enabled == 0x01 + Case (0x00) + { + \_SB.PCI0.LPCB.KLSC = 0x00 + } + Case (0xdd) + { + \_SB.PCI0.LPCB.KLSC = 0x01 + } + } + \_SB.PCI0.LPCB.KLBC = \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLBE)) } -- To view, visit https://review.coreboot.org/c/coreboot/+/62605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62e0fc3b6fcae72f2d8eacf37a390b4e4b1f0783 Gerrit-Change-Number: 62605 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs: Store the correct value for TPLE when suspending
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62604 ) Change subject: ec/starlabs: Store the correct value for TPLE when suspending ...................................................................... ec/starlabs: Store the correct value for TPLE when suspending The current code will read the raw value from the EC, which doesn't match the respective setting in CMOS. Switch argument will store the correct value. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I921be8aea55b95f1ba233d2640d9bae80f8c3703 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62604 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/starlabs/merlin/acpi/suspend.asl 1 file changed, 19 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl index 4389729..9f88a05 100644 --- a/src/ec/starlabs/merlin/acpi/suspend.asl +++ b/src/ec/starlabs/merlin/acpi/suspend.asl @@ -5,8 +5,25 @@ If ((Arg0 == 0x04) || (Arg0 == 0x05)) { /* Store current EC settings in CMOS */ - \_SB.PCI0.LPCB.TPLC = - \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.TPLE)) + Switch (ToInteger (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.TPLE)))) + { + // 0x00 == Enabled == 0x00 + // 0x11 == Re-enabled == 0x00 + // 0x22 == Disabled == 0x01 + Case (0x00) + { + \_SB.PCI0.LPCB.TPLC = 0x00 + } + Case (0x11) + { + \_SB.PCI0.LPCB.TPLC = 0x00 + } + Case (0x22) + { + \_SB.PCI0.LPCB.TPLC = 0x01 + } + } + \_SB.PCI0.LPCB.FLKC = \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.FLKE)) \_SB.PCI0.LPCB.KLSC = -- To view, visit https://review.coreboot.org/c/coreboot/+/62604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I921be8aea55b95f1ba233d2640d9bae80f8c3703 Gerrit-Change-Number: 62604 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/starlabs/labtop: Always run PTS
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62421 ) Change subject: mb/starlabs/labtop: Always run PTS ...................................................................... mb/starlabs/labtop: Always run PTS Remove the dependency on Arg0 so PTS always runs. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I96c44397d62848231039330a32de781f75bb56bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62421 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Andy Pont <andy.pont(a)sdcsystems.com> --- M src/mainboard/starlabs/labtop/acpi/sleep.asl 1 file changed, 1 insertion(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Andy Pont: Looks good to me, but someone else must approve diff --git a/src/mainboard/starlabs/labtop/acpi/sleep.asl b/src/mainboard/starlabs/labtop/acpi/sleep.asl index 9dc818d0..b4df10a 100644 --- a/src/mainboard/starlabs/labtop/acpi/sleep.asl +++ b/src/mainboard/starlabs/labtop/acpi/sleep.asl @@ -2,10 +2,7 @@ Method (MPTS, 1, NotSerialized) { - If (Arg0) - { - RPTS (Arg0) - } + RPTS (Arg0) } Method (MWAK, 1, NotSerialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/62421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96c44397d62848231039330a32de781f75bb56bb Gerrit-Change-Number: 62421 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2022