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Change subject: soc/intel/common: Retry END_OF_POST command
......................................................................
Patch Set 12:
(1 comment)
File src/soc/intel/common/block/cse/cse_eop.c:
https://review.coreboot.org/c/coreboot/+/62192/comment/11477c5d_4b49cf25
PS12, Line 14: #define CSE_MAX_RETRY_CMD 3
I don't think we need a macro for this, do we?
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Change subject: soc/intel/common: Retry END_OF_POST command
......................................................................
Patch Set 12:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62192/comment/fff7015f_7d8e007c
PS12, Line 15: TEST=Verify EOP retry mechanism for brya board.
> Please see above. […]
Let me rephrase: how many tries are actually needed on brya?
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Change subject: mb/google/herobrine: Add trackpad initialization
......................................................................
mb/google/herobrine: Add trackpad initialization
Initialize trackpad on Qualcomm reference boards
BUG=b:182963902,b:223826899
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I93e866d92cf37887a98de88b4b2d768562515670
---
M src/mainboard/google/herobrine/mainboard.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/62226/9
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Change subject: soc/amd/common/block: Add mainboard_handle_smi
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/cpu/smm/smi_handler.c:
https://review.coreboot.org/c/coreboot/+/62598/comment/84d96b94_d087558f
PS1, Line 12: printk(BIOS_WARNING, "SMI event %d is missing handler\n", event);
> Will this be logging unnecessarily for any previously unhandled SMIs?
Hrmm, you bring up a good point. Zork and guybrush don't have any other SMIs currently enabled, so we shouldn't be printing anything. They implement mainboard_smi_gpi to print a message: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
Grunt on the other hand does rely on the GPE SMI: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
It uses the `mainboard_smi_gpi` handler to handle this. So this means that on Grunt when we get the EC SMI, we will print this error, and then below we will handle the SMI. So I think we need to migrate everyone from using `mainboard_smi_gpi` to `mainboard_handle_smi`. That method is defined as part of the SMM handler header: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
So we really can't deprecate it. I guess I can change this weak method to check if the event is a gevent and not log anything. I'll do that.
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Change subject: mb/google/herobrine: Add trackpad initialization
......................................................................
mb/google/herobrine: Add trackpad initialization
BUG=b:182963902,b:223826899
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I93e866d92cf37887a98de88b4b2d768562515670
---
M src/mainboard/google/herobrine/mainboard.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/62226/8
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Change subject: soc/amd/common/block: Add mainboard_handle_smi
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/cpu/smm/smi_handler.c:
https://review.coreboot.org/c/coreboot/+/62598/comment/09ffcf2e_89e78779
PS1, Line 12: printk(BIOS_WARNING, "SMI event %d is missing handler\n", event);
Will this be logging unnecessarily for any previously unhandled SMIs?
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Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62670 )
Change subject: mb/google/guybrush: Enable DEBUG_SMI for non-serial firmware
......................................................................
mb/google/guybrush: Enable DEBUG_SMI for non-serial firmware
In order to copy the PSP verstage logs into x86 cbmem, we need to enable
DEBUG_SMI. This will include the CBMEM console code in SMM. I only
enable DEBUG_SMI when UART is disabled because SMM doesn't currently
save/restore the UART registers. This will result in clearing the
interrupt enable bits and makes it so you can no longer use the TTY.
BUG=b:221231786, b:217968734
BRANCH=guybrush
TEST=Build serial and non serial firmware and verify DEBUG_SMI is set
correctly.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I85a7933e8eb49ff920d00e43a494aaeab555ef3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62670
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/guybrush/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index ecec688..b2cba6e 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -13,6 +13,7 @@
select AMD_SOC_CONSOLE_UART
select BOARD_ROMSIZE_KB_16384
select CONSOLE_CBMEM_DUMP_TO_UART if !CONSOLE_SERIAL
+ select DEBUG_SMI if !CONSOLE_SERIAL # TODO(b/217968734): Always enable
select DISABLE_KEYBOARD_RESET_PIN
select DISABLE_SPI_FLASH_ROM_SHARING
select DRIVERS_ACPI_THERMAL_ZONE
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Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62402 )
Change subject: soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem
......................................................................
soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem
Now that SMM can write to CBMEM we can simply replay the transfer buffer
cbmem console to move it into the main cbmem console.
replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols.
Since the SMM rmodule get linked with a different linker script than
bootblock/romstage it doesn't have access to these symbols. In order to
pass these symbols into SMM, we parse the bootblock.map file and
generate an early_ram.ld script. This script is then used when linking
SMM.
I replay the buffer in `smm_soc_early_init` because this call happens
before `console_init()`. `console_init()` prints the SMM header and we
want to append the verstage contents before printing the header to avoid
confusion.
BUG=b:221231786
TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when
doing `cbmem -c`.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62402
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/cezanne/smihandler.c
M src/soc/amd/common/vboot/Makefile.inc
A src/soc/amd/common/vboot/early_ram_symbols.awk
3 files changed, 34 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c
index 509a1d4..a149e57 100644
--- a/src/soc/amd/cezanne/smihandler.c
+++ b/src/soc/amd/cezanne/smihandler.c
@@ -9,9 +9,11 @@
#include <arch/hlt.h>
#include <arch/io.h>
#include <console/console.h>
+#include <console/cbmem_console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include <elog.h>
+#include <soc/psp_transfer.h>
#include <soc/smi.h>
#include <soc/smu.h>
#include <soc/southbridge.h>
@@ -150,3 +152,9 @@
return NULL;
}
+
+void smm_soc_early_init(void)
+{
+ if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && __CBMEM_CONSOLE_ENABLE__)
+ replay_transfer_buffer_cbmemc();
+}
diff --git a/src/soc/amd/common/vboot/Makefile.inc b/src/soc/amd/common/vboot/Makefile.inc
index 6938d16..e3486ab 100644
--- a/src/soc/amd/common/vboot/Makefile.inc
+++ b/src/soc/amd/common/vboot/Makefile.inc
@@ -7,3 +7,13 @@
bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += vboot_bootblock.c
bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += transfer_buffer.c
+smm-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += transfer_buffer.c
+
+# We don't use the early RAM memlayout linker for SMM, so we don't have access
+# to the early RAM symbols. We manually generate a file that defines the symbols
+# for us.
+$(obj)/smm/early_ram_symbols.ld: $(objcbfs)/bootblock.map $(src)/soc/amd/common/vboot/early_ram_symbols.awk
+ awk -f $(src)/soc/amd/common/vboot/early_ram_symbols.awk -- "$<" > "$@"
+
+$(obj)/smm/smm.elf: $(obj)/smm/early_ram_symbols.ld
+$(obj)/smm/smm.elf-ldflags += -T $(obj)/smm/early_ram_symbols.ld
diff --git a/src/soc/amd/common/vboot/early_ram_symbols.awk b/src/soc/amd/common/vboot/early_ram_symbols.awk
new file mode 100644
index 0000000..85a1627
--- /dev/null
+++ b/src/soc/amd/common/vboot/early_ram_symbols.awk
@@ -0,0 +1,16 @@
+#!/usr/bin/awk -F
+#
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Generates a linker script to provide early RAM symbols.
+#
+# e.g.,
+# _cbmemc_transfer = 0x02014040;
+# _ecbmemc_transfer = 0x02015640;
+# _cbmemc_transfer_size = 0x00001600;
+
+$3 ~ /^_e?transfer_buffer$/ { printf("%s = 0x%s;\n", $3, $1)}
+$3 ~ /^_transfer_buffer_size$/ { printf("%s = 0x%s;\n", $3, $1)}
+
+$3 ~ /^_e?cbmemc_transfer$/ { printf("%s = 0x%s;\n", $3, $1)}
+$3 ~ /^_cbmemc_transfer_size$/ { printf("%s = 0x%s;\n", $3, $1)}
5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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