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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya: Set EPP to 45% for all Brya variants
......................................................................
mb/google/brya: Set EPP to 45% for all Brya variants
This sets EPP value to be 45% for all Brya variants.
Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.
BUG=b:219785001
BRANCH=firmware-brya-14505.B
TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02
---
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/62655/9
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Hello build bot (Jenkins), Cliff Huang, Selma Bensaid, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62655
to look at the new patch set (#8).
Change subject: mb/google/brya: Set EPP to 45% for all Brya variants
......................................................................
mb/google/brya: Set EPP to 45% for all Brya variants
This sets EPP value to be 45% for all brya variants.
Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.
BUG=b:219785001
BRANCH=firmware-brya-14505.B
TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02
---
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/62655/8
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62599 )
Change subject: mb/google/guybrush: Enable EC SMI handler
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62599/comment/be5ec6d3_2d3b46d4
PS1, Line 10: are disabled once ACPI is
: enabled
Just for my knowledge, what component writes to ACPI SMI command port and triggers this ACPI Enable SMI?
File src/mainboard/google/guybrush/smihandler.c:
https://review.coreboot.org/c/coreboot/+/62599/comment/6506a3f3_3725a270
PS1, Line 48: chromeec_smi_process_events();
Does this end up handling the LID_CLOSED event as an SMI event when OS is expected to handle it.
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Change subject: soc/intel/common: Retry END_OF_POST command
......................................................................
Patch Set 12:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62192/comment/08d262c4_631094e4
PS12, Line 11: max 3 times
> ME BWG spec recommends only 3 times, hence I'm retrying thrice (including 1st attempt)
Well, your commit message says something different and even your comment is not consistent :P
*re*tries the EOP command max 3 times == *re*trying thrice != including 1st attempt == trying once, *re*trying twice
*re*trying means try *again*. However, you cannot try *again* if you haven't tried once before. So, actually you're trying once and retrying twice *or* just trying thrice.
(Sorry for nitpicking ;D)
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Change subject: mb/google/herobrine: Add trackpad initialization
......................................................................
Patch Set 9: Code-Review+2
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