coreboot-gerrit March 2022

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Change in coreboot[master]: soc/mediatek/mt8195: Enable PCIe support
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56793 ) Change subject: soc/mediatek/mt8195: Enable PCIe support ...................................................................... soc/mediatek/mt8195: Enable PCIe support Enable PCIe support for mt8195. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56793 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/soc.c 2 files changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig index d1cb09b..dab1590 100644 --- a/src/soc/mediatek/mt8195/Kconfig +++ b/src/soc/mediatek/mt8195/Kconfig @@ -10,6 +10,7 @@ select HAVE_UART_SPECIAL select SOC_MEDIATEK_COMMON select DPM_FOUR_CHANNEL + select PCI if SOC_MEDIATEK_MT8195 diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index d28f668..995aadc 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -2,6 +2,7 @@ #include <bootmem.h> #include <device/device.h> +#include <device/pci.h> #include <soc/apusys.h> #include <soc/devapc.h> #include <soc/dfd.h> @@ -9,6 +10,7 @@ #include <soc/hdmi.h> #include <soc/mcupm.h> #include <soc/mmu_operations.h> +#include <soc/pcie.h> #include <soc/sspm.h> #include <soc/ufs.h> #include <symbols.h> @@ -44,9 +46,19 @@ .init = soc_init, }; +static struct device_operations pci_domain_ops = { + .read_resources = &mtk_pcie_domain_read_resources, + .set_resources = &mtk_pcie_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, + .enable = &mtk_pcie_domain_enable, +}; + static void enable_soc_dev(struct device *dev) { - dev->ops = &soc_ops; + if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + dev->ops = &soc_ops; + else if (dev->path.type == DEVICE_PATH_DOMAIN) + dev->ops = &pci_domain_ops; } struct chip_operations soc_mediatek_mt8195_ops = { 21 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/56793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff Gerrit-Change-Number: 56793 Gerrit-PatchSet: 24 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: Add driver to configure PCIe
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56792 ) Change subject: soc/mediatek/mt8195: Add driver to configure PCIe ...................................................................... soc/mediatek/mt8195: Add driver to configure PCIe Add a new function 'mtk_pcie_pre_init' to assert the PCIe reset at early stage to reduce the impact of 100ms delay. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56792 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/include/soc/pcie.h A src/soc/mediatek/mt8195/pcie.c 3 files changed, 112 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 8ab78a8..68fe0f3 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -70,6 +70,7 @@ ramstage-y += mt6360.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c +ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c ramstage-y += ../common/pll.c pll.c ramstage-y += ../common/pmif.c ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c diff --git a/src/soc/mediatek/mt8195/include/soc/pcie.h b/src/soc/mediatek/mt8195/include/soc/pcie.h new file mode 100644 index 0000000..0978531 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/pcie.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_PCIE_H +#define SOC_MEDIATEK_MT8195_PCIE_H + +#include <soc/pcie_common.h> + +void mtk_pcie_pre_init(void); +void mtk_pcie_get_hw_info(struct mtk_pcie_controller *ctrl); + +#endif diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c new file mode 100644 index 0000000..8a1fca4 --- /dev/null +++ b/src/soc/mediatek/mt8195/pcie.c @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/stdlib.h> +#include <console/console.h> +#include <device/mmio.h> +#include <device/resource.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <soc/pcie.h> +#include <soc/pcie_common.h> +#include <stdlib.h> +#include <string.h> + +#define PCIE_REG_BASE_PORT0 0x112f0000 +#define PCIE_RST_CTRL_REG (PCIE_REG_BASE_PORT0 + 0x148) +#define PCIE_MAC_RSTB BIT(0) +#define PCIE_PHY_RSTB BIT(1) +#define PCIE_BRG_RSTB BIT(2) +#define PCIE_PE_RSTB BIT(3) + + +/* MMIO range (64MB): 0x20000000 ~ 0x24000000 */ +/* Some devices still need io ranges, reserve 16MB for compatibility */ +static const struct mtk_pcie_mmio_res pcie_mmio_res_io = { + .cpu_addr = 0x20000000, + .pci_addr = 0x20000000, + .size = 16 * MiB, + .type = IORESOURCE_IO, +}; + +static const struct mtk_pcie_mmio_res pcie_mmio_res_mem = { + .cpu_addr = 0x21000000, + .pci_addr = 0x21000000, + .size = 48 * MiB, + .type = IORESOURCE_MEM, +}; + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func pcie_pins[2][3] = { + { + PAD_FUNC(PCIE_WAKE_N, WAKEN), + PAD_FUNC(PCIE_PERESET_N, PERSTN), + PAD_FUNC(PCIE_CLKREQ_N, CLKREQN), + }, + { + PAD_FUNC(CMMCLK0, PERSTN_1), + PAD_FUNC(CMMCLK1, CLKREQN_1), + PAD_FUNC(CMMCLK2, WAKEN_1), + }, +}; + +static void mtk_pcie_set_pinmux(uint8_t port) +{ + const struct pad_func *pins = pcie_pins[port]; + size_t i; + + for (i = 0; i < ARRAY_SIZE(pcie_pins[port]); i++) { + gpio_set_mode(pins[i].gpio, pins[i].func); + gpio_set_pull(pins[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + } +} + +static void mtk_pcie_reset(uintptr_t reg, bool enable) +{ + uint32_t val; + + val = read32p(reg); + + if (enable) + val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | + PCIE_PE_RSTB; + else + val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | + PCIE_PE_RSTB); + + write32p(reg, val); +} + +void mtk_pcie_pre_init(void) +{ + mtk_pcie_set_pinmux(0); + + /* Assert all reset signals at early stage */ + mtk_pcie_reset(PCIE_RST_CTRL_REG, true); +} + +void mtk_pcie_get_hw_info(struct mtk_pcie_controller *ctrl) +{ + ctrl->base = PCIE_REG_BASE_PORT0; + ctrl->mmio_res_io = &pcie_mmio_res_io; + ctrl->mmio_res_mem = &pcie_mmio_res_mem; + ctrl->reset = &mtk_pcie_reset; +} 20 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/56792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Gerrit-Change-Number: 56792 Gerrit-PatchSet: 23 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: merged

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Change in coreboot[master]: spd/lp5: Add new part MT62F2G32D8DR-031
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62542 ) Change subject: spd/lp5: Add new part MT62F2G32D8DR-031 ...................................................................... spd/lp5: Add new part MT62F2G32D8DR-031 Micron MT62F2G32D8DR-031 will be used for skyrim P1. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:213926260 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: Iad2bb53de2b54648d5dd66808973f26b1c8a5df7 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62542 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M spd/lp5/memory_parts.json M spd/lp5/set-0/parts_spd_manifest.generated.txt A spd/lp5/set-0/spd-4.hex M spd/lp5/set-1/parts_spd_manifest.generated.txt A spd/lp5/set-1/spd-4.hex 5 files changed, 76 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json index 164d837..37e31d2 100644 --- a/spd/lp5/memory_parts.json +++ b/spd/lp5/memory_parts.json @@ -49,6 +49,16 @@ "ranksPerChannel": 1, "speedMbps": 6400 } + }, + { + "name": "MT62F2G32D8DR-031 WT:B", + "attribs": { + "densityPerDieGb": 8, + "diesPerPackage": 8, + "bitWidthPerChannel": 8, + "ranksPerChannel": 2, + "speedMbps": 6400 + } } ] } diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt index 2d1c643..f6539a2 100644 --- a/spd/lp5/set-0/parts_spd_manifest.generated.txt +++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt @@ -6,3 +6,4 @@ H9JCNNNCP3MLYR-N6E,spd-2.hex K3LKBKB0BM-MGCP,spd-3.hex H9JCNNNBK3MLYR-N6E,spd-1.hex +MT62F2G32D8DR-031 WT:B,spd-4.hex diff --git a/spd/lp5/set-0/spd-4.hex b/spd/lp5/set-0/spd-4.hex new file mode 100644 index 0000000..851957f --- /dev/null +++ b/spd/lp5/set-0/spd-4.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 22 F9 08 00 00 00 00 09 01 00 00 +00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt index 2d1c643..f6539a2 100644 --- a/spd/lp5/set-1/parts_spd_manifest.generated.txt +++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt @@ -6,3 +6,4 @@ H9JCNNNCP3MLYR-N6E,spd-2.hex K3LKBKB0BM-MGCP,spd-3.hex H9JCNNNBK3MLYR-N6E,spd-1.hex +MT62F2G32D8DR-031 WT:B,spd-4.hex diff --git a/spd/lp5/set-1/spd-4.hex b/spd/lp5/set-1/spd-4.hex new file mode 100644 index 0000000..7255eec --- /dev/null +++ b/spd/lp5/set-1/spd-4.hex @@ -0,0 +1,32 @@ +23 11 13 0E 85 21 F9 18 00 40 00 00 09 02 00 00 +00 00 03 00 00 00 00 00 2B 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/62542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad2bb53de2b54648d5dd66808973f26b1c8a5df7 Gerrit-Change-Number: 62542 Gerrit-PatchSet: 5 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne/psp_verstage: Log the platform boot mode report
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62668 ) Change subject: soc/amd/cezanne/psp_verstage: Log the platform boot mode report ...................................................................... soc/amd/cezanne/psp_verstage: Log the platform boot mode report Log the platform boot mode reported by PSP verstage to PSP stage 1 bootloader. This helps to improve the debuggability. BUG=b:193050286 TEST=Build and Boot to OS in Nipperkin. Ensure that the platform boot mode is logged in the verstage logs. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I752ee56f2af48215a770d799432d02f0609757cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62668 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> --- M src/soc/amd/cezanne/psp_verstage/chipset.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c index 41d318e..372fa36 100644 --- a/src/soc/amd/cezanne/psp_verstage/chipset.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bl_uapp/bl_syscall_public.h> +#include <console/console.h> #include <psp_verstage.h> uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) @@ -35,6 +36,8 @@ void platform_report_mode(int developer_mode_enabled) { + printk(BIOS_INFO, "Reporting %s mode\n", + developer_mode_enabled ? "Developer" : "Production"); if (developer_mode_enabled) svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_DEVELOPER); else -- To view, visit https://review.coreboot.org/c/coreboot/+/62668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I752ee56f2af48215a770d799432d02f0609757cd Gerrit-Change-Number: 62668 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRM
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62667 ) Change subject: mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRM ...................................................................... mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRM GPIO_18 is used for LCD_PRIVACY_SCREEN feature starting board phase 2. But it is programmed incorrectly in the concerned ACPI device. Pass the correct GPIO. BUG=b:204401306 TEST=Build and boot to OS in Nipperkin. Ensure that the ACPI object contains the right GPIO. Ensure that the screen visibility gets updated by pressing the privacy screen button. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I99d40b49f4e97063f1ec2e15ac3da21f700a93eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62667 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Rob Barnes: Looks good to me, approved Jon Murphy: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 776edc8..adde71f 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -187,7 +187,7 @@ # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" register "device[0].privacy.enabled" = "1" - register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_5)" + register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_18)" device generic 0.0 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/62667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99d40b49f4e97063f1ec2e15ac3da21f700a93eb Gerrit-Change-Number: 62667 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/adl: Send EOP early in the boot sequence
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62272 ) Change subject: soc/intel/adl: Send EOP early in the boot sequence ...................................................................... soc/intel/adl: Send EOP early in the boot sequence As part of boot time optimization, one of the culprit was CSE where response to End Of Post (EOP) command used to take ~60ms. Earlier patch was pushed to delay the EOP to reduce response time to ~5-7 ms. During this stage overall platform boot time was ~1.15 seconds. Once boot time was optimized to ~ 1 seconds, CSE EOP time again increased to ~80 ms since coreboot used to send EOP at the time where CSE was busy. This created some back and forth moving of sending EOP command function within coreboot sequence. Upon debugging using traces, it was found that coreboot used to send EOP late where CSE was busy loading other IP payload, so it might take more time to respond. In order to avoid delayed response, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible. This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message. Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya board. Note that once SoC code sends EOP, coreboot common code won't send it again since common code already has check in case EOP is sent earlier. BUG=b:211085685 BRANCH=firmware-brya-14505.B TEST=Tested on Brya system before and after the changes. Observed ~40ms savings in boot time. Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62272 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.c 2 files changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Ronak Kanabar: Looks good to me, approved Sridhar Siricilla: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0484b17..38415e6 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -101,6 +101,7 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOC_INTEL_CSE_SEND_EOP_EARLY select SOC_INTEL_CSE_SET_EOP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index b423226..699b39d 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -6,6 +6,7 @@ #include <fsp/util.h> #include <intelblocks/acpi.h> #include <intelblocks/cfg.h> +#include <intelblocks/cse.h> #include <intelblocks/gpio.h> #include <intelblocks/irq.h> #include <intelblocks/itss.h> @@ -148,6 +149,20 @@ /* Swap enabled TBT root ports in device tree if needed. */ pcie_rp_update_devicetree(get_tbt_pcie_rp_table()); + + /* + * Earlier when coreboot used to send EOP at late as possible caused + * issue of delayed response from CSE since CSE was busy loading payload. + * To resolve the issue, EOP should be sent earlier than current sequence + * in the boot sequence at BS_DEV_INIT. + * Intel CSE team recommends to send EOP close to FW init (between FSP-S exit and + * current boot sequence) to reduce message response time from CSE hence moving + * sending EOP to earlier stage. + */ + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY)) { + printk(BIOS_INFO, "Sending EOP early from SoC\n"); + cse_send_end_of_post(); + } } static void cpu_fill_ssdt(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/62272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Gerrit-Change-Number: 62272 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/common/block/cse: Add option to send EOP early via SoC
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60195 ) Change subject: intel/common/block/cse: Add option to send EOP early via SoC ...................................................................... intel/common/block/cse: Add option to send EOP early via SoC Earlier while trying to optimize boot time End Of Post (EOP) time kept increasing (~80 ms) when boot time decreased to around 1 second. This was because CSE was busy with own firmware loading. When EOP was moved later in boot stage it again created issue since CSE got busy with other payload loading for OS boot, so response to EOP got delayed by ~70-80 ms. In order to avoid delayed response, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible. This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message. Moving EOP to BS_DEV_INIT boot state meets this requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya QS board. Since this setting might vary for each SoC, SoCs can decide when to send EOP in the boot sequence. This patch adds Kconfig option to send EOP via SoC BUG=b:211085685 BRANCH=firmware-brya-14505.B TEST=Code compilation is fine for Brya board. Boot time test is done using entire patchset and EOP time is reduced to ~25ms from earlier ~80ms. Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60195 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Ronak Kanabar: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index fb75486..e302447 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -45,6 +45,15 @@ Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) to make `HECI1` device disable using private configuration register (PCR) write. +config SOC_INTEL_CSE_SEND_EOP_EARLY + bool + depends on SOC_INTEL_COMMON_BLOCK_CSE + help + Use this config to send End Of Post (EOP) earlier through SoC code in order to + reduce time required to send EOP and getting CSE response. + In later stages, CSE might be busy and might require more time to process EOP command. + SoC can use this Kconfig to send EOP earlier by itself. + config SOC_INTEL_CSE_LITE_SKU bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/60195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35 Gerrit-Change-Number: 60195 Gerrit-PatchSet: 13 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run se...
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61498 ) Change subject: Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially" ...................................................................... Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially" This reverts commit 6af980a2aeca9b8cedfb3d7734389e6e36099c88. BUG=b:199246420 Change-Id: Iddb7aa6d52b563485a496798f2fe31ed64b4f4a8 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61498 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c 1 file changed, 4 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Maulik V Vaghela: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index 9aef1b6..50e35b0 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -94,23 +94,10 @@ /* Run on BSP */ procedure(argument); - /* - * Run on APs Serially - * - * FIXME: As per MP service specification, EDK2 is allowed to specify the mode - * in which a 'func' routine should be executed on APs (i.e. execute serially - * or concurrently). - * - * MP service API `StartupAllCPUs` doesn't specify such requirement. - * Hence, running the `CpuCacheInfoCollectCoreAndCacheData` - * (UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c#194) - * simultaneously on APs results in a coherency issue (hang while executing `func`) - * due to lack of acquiring a spin lock while accessing common data structure in - * multiprocessor environment. - */ - if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, false) != - CB_SUCCESS) { - printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); + /* Run on APs */ + if (mp_run_on_aps((void *)procedure, argument, + MP_RUN_ON_ALL_CPUS, timeout_usec) != CB_SUCCESS) { + printk(BIOS_ERR, "%s: Exit with Failure\n", __func__); return FSP_NOT_STARTED; } -- To view, visit https://review.coreboot.org/c/coreboot/+/61498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddb7aa6d52b563485a496798f2fe31ed64b4f4a8 Gerrit-Change-Number: 61498 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62478 ) Change subject: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave ...................................................................... mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave The Brask DDR4 setting are interleave, due to Moli PCB layer limited and the routing need to smooth, we will use non-interleave for Moli DDR4. BUG=b:219831754 Signed-off-by: zoey wu <zoey_wu(a)wistron.corp-partner.google.com> Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62478 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Zhuohao Lee <zhuohao(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/brya/variants/moli/Makefile.inc A src/mainboard/google/brya/variants/moli/memory.c 2 files changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, approved Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/moli/Makefile.inc b/src/mainboard/google/brya/variants/moli/Makefile.inc index aa151d6..f5c5897 100644 --- a/src/mainboard/google/brya/variants/moli/Makefile.inc +++ b/src/mainboard/google/brya/variants/moli/Makefile.inc @@ -1,6 +1,7 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c ramstage-y += gpio.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/moli/memory.c b/src/mainboard/google/brya/variants/moli/memory.c new file mode 100644 index 0000000..ad33e9c --- /dev/null +++ b/src/mainboard/google/brya/variants/moli/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {50, 20, 25, 25, 25}, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .ddr_config = { + .dq_pins_interleaved = false, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &ddr4_mem_config; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d Gerrit-Change-Number: 62478 Gerrit-PatchSet: 6 Gerrit-Owner: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brask/variants/moli: Reduce PSysMax to 11 A
by Felix Held (Code Review) 10 Mar '22

10 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62374 ) Change subject: mb/google/brask/variants/moli: Reduce PSysMax to 11 A ...................................................................... mb/google/brask/variants/moli: Reduce PSysMax to 11 A Decrease PSysMax from 13.52 A to 11 A for Moli variant according to its power circuitry, implying Psys_Pmax = 11A * 19.5V = 214.5W BUG=b:215258941 Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: I61f4813f3527123a590d80b4a6e49d76ebb71c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62374 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/brya/variants/moli/Makefile.inc A src/mainboard/google/brya/variants/moli/ramstage.c 2 files changed, 39 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/moli/Makefile.inc b/src/mainboard/google/brya/variants/moli/Makefile.inc index 6c29346..aa151d6 100644 --- a/src/mainboard/google/brya/variants/moli/Makefile.inc +++ b/src/mainboard/google/brya/variants/moli/Makefile.inc @@ -3,3 +3,4 @@ romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/moli/ramstage.c b/src/mainboard/google/brya/variants/moli/ramstage.c new file mode 100644 index 0000000..5690156 --- /dev/null +++ b/src/mainboard/google/brya/variants/moli/ramstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DID_INTEL_ADL_P_ID_10, 15, 135 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 135 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 135 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 230 }, +}; + +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 11000, + .bj_volts_mv = 19500 +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61f4813f3527123a590d80b4a6e49d76ebb71c99 Gerrit-Change-Number: 62374 Gerrit-PatchSet: 14 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit March 2022