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Change subject: mb/google/corsola: Revise power-on sequence of PS8640
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/corsola/display.c:
https://review.coreboot.org/c/coreboot/+/62893/comment/07a2d572_d1adfcb6
PS6, Line 32: mdelay(55);
> Users might want to install upstream firmware themselves with different payloads. But your call. […]
Thanks for suggestion.
I add the power-on sequence and datasheet name in driver comment.
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Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62893
to look at the new patch set (#8).
Change subject: mb/google/corsola: Revise power-on sequence of PS8640
......................................................................
mb/google/corsola: Revise power-on sequence of PS8640
Although the panel initializes fine and the fw recovery screen is
displayed without issues, the current power-on sequence of the
PS8640 violates the spec of the PS8640, which can be confirmed by
measuring it with an oscilloscope.
The sequence is:
- set VDD12 to be 1.2V
- set VDD33 to be 3.3V
- pull hign PD#
- pull down RST#
- delay 2ms
- pull high RST#
- delay more than 50ms (55ms for margin)
- pull down RST#
- delay more than 50ms (55ms for margin)
- pull high RST#
This flow will increase 110ms if firmware display is enabled in
krabby. For normal booting flow, the firmware will not be enabled,
so it will meet boot time requirements of Chrome OS. (Less than 1s.)
Datasheet name: PS8640_DS_V1.4_20200210.docx.
Chapter: 14.
BUG=b:222650141
TEST=show fw display normally in krabby.
TEST=result of waveform meets the spec.
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3
---
M src/mainboard/google/corsola/display.c
1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/62893/8
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62893 )
Change subject: mb/google/corsola: Revise power-on sequence of PS8640
......................................................................
Patch Set 7: Code-Review+1
(1 comment)
File src/mainboard/google/corsola/display.c:
https://review.coreboot.org/c/coreboot/+/62893/comment/050e094d_6740eaef
PS6, Line 32: mdelay(55);
> This patch is verified and it looks good from waveform. […]
Users might want to install upstream firmware themselves with different payloads. But your call. (It’s now in the commit message, but maybe a comment should be added to the code, that at least 50 ms is specified in the datasheet.)
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Change subject: mb/google/corsola: Revise power-on sequence of PS8640
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS6:
> Sorry for all my nitpicks. Thank you for responding so quickly.
no problem. Thanks for your review.
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Ben Chuang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62917 )
Change subject: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
......................................................................
drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
Add an option to set L1 entry delay to Max for GL9763E. The L1 entry delay will
be changed to expected value by sdhci-pci-gli driver in Linux.
BUG=b:220079865
TEST=Verify GL9763 L1 entry delay is Max in coreboot
Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601
Signed-off-by: Ben Chuang <benchuanggli(a)gmail.com>
---
M src/drivers/genesyslogic/gl9763e/Kconfig
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/genesyslogic/gl9763e/gl9763e.h
3 files changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/62917/1
diff --git a/src/drivers/genesyslogic/gl9763e/Kconfig b/src/drivers/genesyslogic/gl9763e/Kconfig
index c254707..555ad91 100644
--- a/src/drivers/genesyslogic/gl9763e/Kconfig
+++ b/src/drivers/genesyslogic/gl9763e/Kconfig
@@ -1,2 +1,8 @@
config DRIVERS_GENESYSLOGIC_GL9763E
- bool
+ bool "Genesys Logic GL9763E"
+ default n
+
+config DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX
+ bool "Set L1 entry delay to MAX"
+ depends on DRIVERS_GENESYSLOGIC_GL9763E
+ default n
diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.c b/src/drivers/genesyslogic/gl9763e/gl9763e.c
index 4dcfbdc..4e7be41 100644
--- a/src/drivers/genesyslogic/gl9763e/gl9763e.c
+++ b/src/drivers/genesyslogic/gl9763e/gl9763e.c
@@ -23,6 +23,12 @@
pci_or_config32(dev, SCR, SCR_AXI_REQ);
/* Disable L0s support */
pci_and_config32(dev, CFG_REG_2, ~CFG_REG_2_L0S);
+
+ if (CONFIG(DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX)) {
+ /* Set L1 entry delay to MAX */
+ pci_or_config32(dev, CFG_REG_2, CFG_REG_2_L1DLY_MAX);
+ }
+
/* Set SSC to 30000 ppm */
pci_update_config32(dev, PLL_CTL_2, ~PLL_CTL_2_MAX_SSC_MASK, MAX_SSC_30000PPM);
/* Enable SSC */
diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.h b/src/drivers/genesyslogic/gl9763e/gl9763e.h
index 7f5dbf9..647920c 100644
--- a/src/drivers/genesyslogic/gl9763e/gl9763e.h
+++ b/src/drivers/genesyslogic/gl9763e/gl9763e.h
@@ -14,6 +14,7 @@
#define CFG_REG_2 0x8A4
#define CFG_REG_2_L0S BIT(11)
+#define CFG_REG_2_L1DLY_MAX (0x3FF << 19)
#define PLL_CTL 0x938
#define PLL_CTL_SSC BIT(19)
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Change subject: mb/google/brya/var/banshee: Add mic mute switch setting
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62804/comment/bd905fcd_be9874c1
PS5, Line 13: TEST=emerge-brya coreboot chromeos-bootimage
any evtest log?
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Change subject: mb/google/brya/var/banshee: Add mic mute switch setting
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/banshee/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62804/comment/64a47e64_51d45913
PS5, Line 328: register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_F19)"
Is this intended?
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Change subject: mb/google/brya/var/banshee: Add mic mute switch setting
......................................................................
Patch Set 5:
This change is ready for review.
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Change subject: mb/google/corsola: Revise power-on sequence of PS8640
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62893/comment/f5003a32_075f29a9
PS5, Line 9: The power-on sequence of PS8640 needs to be modified because the
: waveform of power-on sequence do not meet the spec of PS8640.
> Could you clarify that in the commit message? […]
Done
File src/mainboard/google/corsola/display.c:
https://review.coreboot.org/c/coreboot/+/62893/comment/b10b485e_b65d7964
PS6, Line 32: mdelay(55);
> As no problems are known, I’d use 50 ms and not add a margin.
This patch is verified and it looks good from waveform.
I think I still prefer to use 55ms.
After all, it does not matter the boot time requirements of Chrome OS
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Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62893
to look at the new patch set (#7).
Change subject: mb/google/corsola: Revise power-on sequence of PS8640
......................................................................
mb/google/corsola: Revise power-on sequence of PS8640
Although the panel initializes fine and the fw recovery screen is
displayed without issues, the current power-on sequence of the
PS8640 violates the spec of the PS8640, which can be confirmed by
measuring it with an oscilloscope.
The sequence is:
- set VDD12 to be 1.2V
- set VDD33 to be 3.3V
- pull hign PD#
- pull down RST#
- delay 2ms
- pull high RST#
- delay more than 50ms (55ms for margin)
- pull down RST#
- delay more than 50ms (55ms for margin)
- pull high RST#
This flow will increase 110ms if firmware display is enabled in
krabby. For normal booting flow, the firmware will not be enabled,
so it will meet boot time requirements of Chrome OS. (Less than 1s.)
Datasheet name: PS8640_DS_V1.4_20200210.docx.
Chapter: 14.
BUG=b:222650141
TEST=show fw display normally in krabby.
TEST=result of waveform meets the spec.
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3
---
M src/mainboard/google/corsola/display.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/62893/7
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Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Gerrit-MessageType: newpatchset