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Change subject: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
......................................................................
drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
Add an option to set L1 entry delay to Max for GL9763E. The L1 entry
delay will be changed to expected value by sdhci-pci-gli driver in
Linux v5.14.
BUG=b:220079865
TEST=build and verify the value of GL9763E's 0x8A4[28:19] register is
0x3FF.
Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601
Signed-off-by: Ben Chuang <benchuanggli(a)gmail.com>
---
M src/drivers/genesyslogic/gl9763e/Kconfig
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/genesyslogic/gl9763e/gl9763e.h
3 files changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/62917/3
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Change subject: ec/starlabs/merlin: Correct Q event for CPU DN SPEED
......................................................................
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Change subject: payloads/tianocore: Add missing CONFIG_
......................................................................
Patch Set 3: Code-Review+2
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I'd like you to reexamine a change. Please visit
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Change subject: payloads/tianocore: Add missing CONFIG_
......................................................................
payloads/tianocore: Add missing CONFIG_
Add missing CONFIG_ to the Boot Timeout parameter.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I88f4aa0286a77f6c94b5e5ec97a0034ea7594b4f
---
M payloads/external/tianocore/Makefile
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/62920/3
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Change subject: [WIP] drivers/mrc_cache: Drop get_write_protect_state() stubs
......................................................................
[WIP] drivers/mrc_cache: Drop get_write_protect_state() stubs
It should be optional to protect MRC_CACHE without
CHROMEOS so MRC_SETTINGS_PROTECT cannot be enforced
from soc/.
This change selects MRC_SETTINGS_PROTECT also for older
platforms when CHROMEOS is selected.
If a board does not implement get_write_protect_state()
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related SPI flash pages will not get protected.
Currently, such real implementations may or may not be
guarded with CONFIG(CHROMEOS) and the protection is
only expected to work after followup works.
Change-Id: I8db0394645df1917b686339fa79432ccfc6960a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/drivers/mrc_cache/mrc_cache.c
M src/ec/lenovo/h8/vboot.c
M src/mainboard/amd/chausie/chromeos.c
M src/mainboard/amd/majolica/chromeos.c
M src/mainboard/google/foster/chromeos.c
M src/mainboard/intel/adlrvp/chromeos.c
M src/mainboard/intel/coffeelake_rvp/chromeos.c
M src/mainboard/intel/galileo/vboot.c
M src/mainboard/intel/glkrvp/chromeos.c
M src/mainboard/intel/icelake_rvp/chromeos.c
M src/mainboard/intel/jasperlake_rvp/chromeos.c
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/tglrvp/chromeos.c
M src/mainboard/intel/wtm2/chromeos.c
M src/security/vboot/bootmode.c
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/skylake/Kconfig
M src/soc/intel/tigerlake/Kconfig
M src/vendorcode/google/chromeos/Kconfig
25 files changed, 4 insertions(+), 98 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/58968/4
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I'd like you to reexamine a change. Please visit
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Change subject: [RFC] ChromeOS: Declare CHROMEOS_NO_GPIOS
......................................................................
[RFC] ChromeOS: Declare CHROMEOS_NO_GPIOS
Implementation of fill_lb_gpios() is not about VBOOT
but providing payload with information of bootmode.
Change-Id: I9f1eaaeffe388a7f8a7fc2430b6593eb8298461b
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/lib/coreboot_table.c
M src/mainboard/amd/chausie/Kconfig
M src/mainboard/amd/chausie/chromeos.c
M src/mainboard/amd/majolica/Kconfig
M src/mainboard/amd/majolica/chromeos.c
M src/mainboard/google/corsola/Kconfig
M src/mainboard/google/mistral/Kconfig
M src/mainboard/google/mistral/Makefile.inc
M src/security/vboot/bootmode.c
M src/vendorcode/google/chromeos/Kconfig
10 files changed, 11 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/58956/4
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Change subject: payloads/tianocore: Fix Boot Timeout build parameter
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Change subject: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
......................................................................
Patch Set 2: Code-Review+1
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Change subject: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62917/comment/ce136a2e_042a176b
PS2, Line 10: Linux
Please mention the version.
https://review.coreboot.org/c/coreboot/+/62917/comment/4bd70ef6_72486b59
PS2, Line 9: Add an option to set L1 entry delay to Max for GL9763E. The L1 entry delay will
: be changed to expected value by sdhci-pci-gli driver in Linux.
Please use 72 characters per line.
https://review.coreboot.org/c/coreboot/+/62917/comment/c31c4e55_827b580a
PS2, Line 13: TEST=Verify GL9763 L1 entry delay is Max in coreboot
How?
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