coreboot-gerrit March 2022

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Change in coreboot[master]: soc/mediatek: Set soc_ops.set_resources as no-op
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62785 ) Change subject: soc/mediatek: Set soc_ops.set_resources as no-op ...................................................................... soc/mediatek: Set soc_ops.set_resources as no-op Without setting the set_resources field for soc_ops, we will get an error during device initialization: [ERROR] CPU_CLUSTER: 0 missing set_resources Because the set_resources field is considered mandatory, explicitly set it as no-op noop_set_resources. BUG=b:224419346 TEST=emerge-corsola coreboot TEST=Did not see the error on krabby BRANCH=none Change-Id: Ic82b86f0482a9de09e942c1674be5f0ac615851f Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62785 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/mt8173/soc.c M src/soc/mediatek/mt8183/soc.c M src/soc/mediatek/mt8186/soc.c M src/soc/mediatek/mt8192/soc.c M src/soc/mediatek/mt8195/soc.c 5 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Hung-Te Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8173/soc.c b/src/soc/mediatek/mt8173/soc.c index ef57130..7a4eeb6 100644 --- a/src/soc/mediatek/mt8173/soc.c +++ b/src/soc/mediatek/mt8173/soc.c @@ -21,6 +21,7 @@ static struct device_operations soc_ops = { .read_resources = soc_read_resources, + .set_resources = noop_set_resources, .init = soc_init, }; diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index 6bcd4d0..c2e7d26 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -23,6 +23,7 @@ static struct device_operations soc_ops = { .read_resources = soc_read_resources, + .set_resources = noop_set_resources, .init = soc_init, }; diff --git a/src/soc/mediatek/mt8186/soc.c b/src/soc/mediatek/mt8186/soc.c index 7686986..53e5065 100644 --- a/src/soc/mediatek/mt8186/soc.c +++ b/src/soc/mediatek/mt8186/soc.c @@ -32,6 +32,7 @@ static struct device_operations soc_ops = { .read_resources = soc_read_resources, + .set_resources = noop_set_resources, .init = soc_init, }; diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 006a212..cf1fe48 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -37,6 +37,7 @@ static struct device_operations soc_ops = { .read_resources = soc_read_resources, + .set_resources = noop_set_resources, .init = soc_init, }; diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index 995aadc..cf9f412 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -43,6 +43,7 @@ static struct device_operations soc_ops = { .read_resources = soc_read_resources, + .set_resources = noop_set_resources, .init = soc_init, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/62785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic82b86f0482a9de09e942c1674be5f0ac615851f Gerrit-Change-Number: 62785 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/banshee: Replace amp max98357 with max98360
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62887 ) Change subject: mb/google/brya/var/banshee: Replace amp max98357 with max98360 ...................................................................... mb/google/brya/var/banshee: Replace amp max98357 with max98360 Based on the latest schematic, replace amp max98357 with max98360. BUG=b:224692387, b:216110896 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: Id265a4276c3f8b5553a0e5d7ed824b1d9a520d44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62887 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/banshee/gpio.c M src/mainboard/google/brya/variants/banshee/overridetree.cb 2 files changed, 17 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/banshee/gpio.c b/src/mainboard/google/brya/variants/banshee/gpio.c index 75a2743..a6f6854 100644 --- a/src/mainboard/google/brya/variants/banshee/gpio.c +++ b/src/mainboard/google/brya/variants/banshee/gpio.c @@ -229,26 +229,29 @@ /* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */ /* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */ /* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */ - /* R4 : HDA_RST# ==> I2S_SPKR_SCLK_R */ - /* R5 : HDA_SDI1 ==> I2S_SPKR_SFRM_R */ - /* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */ + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), /* R7 : I2S2_RXD ==> NC */ PAD_NC(GPP_R7, NONE), - /* S0 : SNDW0_CLK ==> NC */ - PAD_NC(GPP_S0, NONE), - /* S1 : SNDW0_DATA ==> NC */ - PAD_NC(GPP_S1, NONE), - /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ - /* S3 : SNDW1_DATA ==> DMIC_DATA0_R */ + /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), + /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), + /* S2 : SNDW1_CLK ==> I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), + /* S3 : SNDW1_DATA ==> NC */ + PAD_NC(GPP_S3, NONE), /* S4 : SNDW2_CLK ==> NC */ PAD_NC(GPP_S4, NONE), /* S5 : SNDW2_DATA ==> NC */ PAD_NC(GPP_S5, NONE), - /* S6 : SNDW3_CLK ==> NC */ - PAD_NC(GPP_S6, NONE), - /* S7 : SNDW3_DATA ==> NC */ - PAD_NC(GPP_S7, NONE), + /* S6 : SNDW3_CLK ==> DMIC_CLK0_R */ + /* S7 : SNDW3_DATA ==> DMIC_DATA0_R */ }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index ffc084f..ea81874 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -217,7 +217,7 @@ end device ref hda on chip drivers/generic/max98357a - register "hid" = ""MX98357A"" + register "hid" = ""MX98360A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" register "sdmode_delay" = "5" -- To view, visit https://review.coreboot.org/c/coreboot/+/62887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id265a4276c3f8b5553a0e5d7ed824b1d9a520d44 Gerrit-Change-Number: 62887 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/galtic: update Wifi SAR for for galnat
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62704 ) Change subject: mb/google/dedede/var/galtic: update Wifi SAR for for galnat ...................................................................... mb/google/dedede/var/galtic: update Wifi SAR for for galnat Add wifi sar for galnat/galnat360 Use SKU ID to load wifi table. Each Project and SKU ID correspond as below galtic (sku id:0x120000) galith (sku id:0x130000) galnat (sku id:0x140000)* gallop (sku id:0x150000) galtic360 (sku id:0x260000) galith360 (sku id:0x270000) galnat360 (sku id:0x2B0000)* BUG=b:222008376 TEST=emerge-dedede coreboot chromeos-bootimage \ coreboot-private-files-baseboard-dedede verify the SAR table is correct in each project Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I868a7416a002732736cabea48ce80548ea75e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62704 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/galtic/variant.c 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Frank Chu: Looks good to me, but someone else must approve Ivan Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/galtic/variant.c b/src/mainboard/google/dedede/variants/galtic/variant.c index 558cba6..1e62f0c 100644 --- a/src/mainboard/google/dedede/variants/galtic/variant.c +++ b/src/mainboard/google/dedede/variants/galtic/variant.c @@ -9,12 +9,16 @@ GALTIC_SKU_END = 0x12ffff, GALITH_SKU_START = 0x130000, GALITH_SKU_END = 0x13ffff, + GALNAT_SKU_START = 0x140000, + GALNAT_SKU_END = 0x14ffff, GALLOP_SKU_START = 0x150000, GALLOP_SKU_END = 0x15ffff, GALTIC360_SKU_START = 0x260000, GALTIC360_SKU_END = 0x26ffff, GALITH360_SKU_START = 0x270000, GALITH360_SKU_END = 0x27ffff, + GALNAT360_SKU_START = 0x2B0000, + GALNAT360_SKU_END = 0x2Bffff, }; const char *get_wifi_sar_cbfs_filename(void) { @@ -22,10 +26,14 @@ if (sku_id >= GALTIC_SKU_START && sku_id <= GALTIC_SKU_END) return "wifi_sar-galtic.hex"; + if (sku_id >= GALNAT_SKU_START && sku_id <= GALNAT_SKU_END) + return "wifi_sar-galnat.hex"; if (sku_id >= GALTIC360_SKU_START && sku_id <= GALTIC360_SKU_END) return "wifi_sar-galtic360.hex"; if (sku_id >= GALITH360_SKU_START && sku_id <= GALITH360_SKU_END) return "wifi_sar-galith360.hex"; + if (sku_id >= GALNAT360_SKU_START && sku_id <= GALNAT360_SKU_END) + return "wifi_sar-galnat360.hex"; return WIFI_SAR_CBFS_DEFAULT_FILENAME; } 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I868a7416a002732736cabea48ce80548ea75e517 Gerrit-Change-Number: 62704 Gerrit-PatchSet: 7 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: commonlib/bsd: Add struct name "mem_chip_channel" for external access
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62850 ) Change subject: commonlib/bsd: Add struct name "mem_chip_channel" for external access ...................................................................... commonlib/bsd: Add struct name "mem_chip_channel" for external access struct mem_chip_info { ... struct { --> If no struct name, can't access the channel structure ... } channel[0]; }; BUG=b:182963902,b:177917361 TEST=Build pass on Kingler Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Change-Id: I8dcd3b52f33f80afb7885ffdcad826d86b54b543 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62850 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h index 7194f70..8dc6db3 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h +++ b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h @@ -15,7 +15,7 @@ uint8_t type; /* enum mem_chip_type */ uint8_t num_channels; uint8_t reserved[6]; - struct { + struct mem_chip_channel { uint64_t density; uint8_t io_width; uint8_t manufacturer_id; 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dcd3b52f33f80afb7885ffdcad826d86b54b543 Gerrit-Change-Number: 62850 Gerrit-PatchSet: 5 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork/var/dirinboz: Add fw_config probe for ALC5682-VD & VS
by Rob Barnes (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Paul Menzel, Robert Chen. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61781 ) Change subject: mb/google/zork/var/dirinboz: Add fw_config probe for ALC5682-VD & VS ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd4321ec0a284e35511dd4b860a16506f54cf663 Gerrit-Change-Number: 61781 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 15:40:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/gumboz: Add fw_config probe for ALC5682-VD & VS
by Rob Barnes (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Robert Chen. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61782 ) Change subject: mb/google/zork/var/gumboz: Add fw_config probe for ALC5682-VD & VS ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b0231a3ee9c0dad289ffd50607b3ae6201f56a0 Gerrit-Change-Number: 61782 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 15:40:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/volmar: Disable thunderbolt
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62810 ) Change subject: mb/google/brya/var/volmar: Disable thunderbolt ...................................................................... mb/google/brya/var/volmar: Disable thunderbolt Volmar does not support Thunderbolt, therefore disable all of the TBT devices in the devicetree. The volmar fit image had been disabled already, cf. chrome-internal:4459289. BUG=b:2233193 TEST=Build and run on DUT. Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62810 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/volmar/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified David Wu: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb index d8bcdbd..5034d6c 100644 --- a/src/mainboard/google/brya/variants/volmar/overridetree.cb +++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb @@ -84,6 +84,11 @@ }" device domain 0 on + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + device ref tcss_dma0 off end + device ref tcss_dma1 off end device ref dtt on chip drivers/intel/dptf ## sensor information 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e Gerrit-Change-Number: 62810 Gerrit-PatchSet: 8 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kinox: Reconfigure GPIO settings
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62749 ) Change subject: mb/google/brya/var/kinox: Reconfigure GPIO settings ...................................................................... mb/google/brya/var/kinox: Reconfigure GPIO settings Configure GPIOs according to updated schematics. - GPP_A21 from NC to TCP_DP1_CTRLCLK. - GPP_A22 from NC to TCP_DP1_CTRLDATA. - GPP_E22 from DDIA_DP_CTRLCLK to NC. - GPP_E23 from DDIA_DP_CTRLDATA to NC. BUG=b:214025396 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I9d2d73820fbb191b682713e4e351c6375927ddf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62749 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/kinox/gpio.c 1 file changed, 4 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kinox/gpio.c b/src/mainboard/google/brya/variants/kinox/gpio.c index fa63c1d..ce55693 100644 --- a/src/mainboard/google/brya/variants/kinox/gpio.c +++ b/src/mainboard/google/brya/variants/kinox/gpio.c @@ -16,10 +16,10 @@ PAD_NC(GPP_A19, NONE), /* A20 : DDSP_HPD2 ==> NC */ PAD_NC(GPP_A20, NONE), - /* A21 : DDPC_CTRCLK ==> NC */ - PAD_NC(GPP_A21, NONE), - /* A22 : DDPC_CTRLDATA ==> NC */ - PAD_NC(GPP_A22, NONE), + /* A21 : DDPC_CTRCLK ==> TCP_DP1_CTRLCLK */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + /* A22 : DDPC_CTRLDATA ==> TCP_DP1_CTRLDATA */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* B2 : VRALERT# ==> TP153 */ PAD_NC(GPP_B2, NONE), @@ -56,10 +56,6 @@ PAD_NC(GPP_E20, NONE), /* E21 : DDP2_CTRLDATA ==> NC */ PAD_NC(GPP_E21, NONE), - /* E22 : DDPA_CTRLCLK ==> DDIA_DP_CTRLCLK */ - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), - /* E23 : DDPA_CTRLDATA ==> DDIA_DP_CTRLDATA */ - PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* F11 : THC1_SPI2_CLK ==> NC */ PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d2d73820fbb191b682713e4e351c6375927ddf4 Gerrit-Change-Number: 62749 Gerrit-PatchSet: 4 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62744 ) Change subject: mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants ...................................................................... mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants This sets EPP value to be 45% for all Adl RVP variants. Historically, EPP Ratio has always been 50% (128) on Chrome platforms. But on Intel Alderlake EPP ratio of 45% is recommended for optimal power and performance on Chrome platforms. TEST= Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73. Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62744 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb 3 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index a4f8594..8847d88 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -168,6 +168,10 @@ register "cnvi_bt_audio_offload" = "true" + # set EPP to 45%: 45 * 256/100 = 115 = 0x73 + register "enable_energy_perf_pref" = "true" + register "energy_perf_pref_value" = "0x73" + # Intel Common SoC Config register "common_soc_config" = "{ .i2c[0] = { diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 4a41df6..deff4dc 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -143,6 +143,10 @@ register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" + # set EPP to 45%: 45 * 256/100 = 115 = 0x73 + register "enable_energy_perf_pref" = "true" + register "energy_perf_pref_value" = "0x73" + # Intel Common SoC Config register "common_soc_config" = "{ .gspi[1] = { diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index d38c010..2b7eca6 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -127,6 +127,10 @@ register "cnvi_bt_audio_offload" = "true" + # set EPP to 45%: 45 * 256/100 = 115 = 0x73 + register "enable_energy_perf_pref" = "true" + register "energy_perf_pref_value" = "0x73" + # Intel Common SoC Config register "common_soc_config" = "{ .i2c[0] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/62744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935 Gerrit-Change-Number: 62744 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/vell: Change AMP driver setting
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60331 ) Change subject: mb/google/brya/var/vell: Change AMP driver setting ...................................................................... mb/google/brya/var/vell: Change AMP driver setting 1.Change I2S GPP_Sx (S0-S3) Native PAD Configuration from NF2 to NF4 2.Select CS35l53 AMP driver for Vell variant. Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c Signed-off-by: Shon.Wang <shon.wang(a)quanta.corp-partner.google.com> Signed-off-by: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60331 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/vell/gpio.c M src/mainboard/google/brya/variants/vell/overridetree.cb 3 files changed, 44 insertions(+), 31 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 9bf50ae..e29ef9f 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -156,10 +156,11 @@ config BOARD_GOOGLE_VELL bool "-> Vell" select BOARD_GOOGLE_BASEBOARD_BRYA + select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GFX_GENERIC select DRIVERS_INTEL_MIPI_CAMERA + select DRIVERS_I2C_CS35L53 select SOC_INTEL_COMMON_BLOCK_IPU - select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_VOLMAR bool "-> Volmar" diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c index e6588b9..e9600da 100644 --- a/src/mainboard/google/brya/variants/vell/gpio.c +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -72,13 +72,13 @@ PAD_NC(GPP_R7, NONE), /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* S3 : SNDW1_DATA ==> I2S_PCH_RX_SPKR_TX */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* S4 : SNDW2_CLK ==> NC */ PAD_NC(GPP_S4, NONE), /* S5 : SNDW2_DATA ==> NC */ diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 4199cec..3af3164 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -172,33 +172,45 @@ end end device ref i2c0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Headset Codec"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_count" = "1" - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on - probe AUDIO MAX98360_ALC5682I_I2S - end + chip drivers/i2c/cs35l53 + register "name" = ""SPK0"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_D14)" + register "boost_type" = "EXTERNAL_BOOST" + register "asp_sdout_hiz" = "ASP_SDOUT_LOGIC0_UNUSED_LOGIC0_DISABLED" + register "gpio1_output_enable" = "true" + register "gpio1_src_select" = "GPIO1_SRC_GPIO" + register "gpio2_src_select" = "GPIO2_SRC_HIGH_IMPEDANCE" + device i2c 0x40 on end end - chip drivers/i2c/generic - register "hid" = ""RTL5682"" - register "name" = ""RT58"" - register "desc" = ""Headset Codec"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_count" = "1" - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on - probe AUDIO MAX98360_ALC5682IVS_I2S - end + chip drivers/i2c/cs35l53 + register "name" = ""SPK1"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_D14)" + register "boost_type" = "EXTERNAL_BOOST" + register "asp_sdout_hiz" = "ASP_SDOUT_LOGIC0_UNUSED_LOGIC0_DISABLED" + register "gpio1_output_enable" = "true" + register "gpio1_src_select" = "GPIO1_SRC_GPIO" + register "gpio2_src_select" = "GPIO2_SRC_HIGH_IMPEDANCE" + device i2c 0x41 on end + end + chip drivers/i2c/cs35l53 + register "name" = ""SPK2"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_D14)" + register "boost_type" = "EXTERNAL_BOOST" + register "asp_sdout_hiz" = "ASP_SDOUT_LOGIC0_UNUSED_LOGIC0_DISABLED" + register "gpio1_output_enable" = "true" + register "gpio1_src_select" = "GPIO1_SRC_GPIO" + register "gpio2_src_select" = "GPIO2_SRC_HIGH_IMPEDANCE" + device i2c 0x42 on end + end + chip drivers/i2c/cs35l53 + register "name" = ""SPK3"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_D14)" + register "boost_type" = "EXTERNAL_BOOST" + register "asp_sdout_hiz" = "ASP_SDOUT_LOGIC0_UNUSED_LOGIC0_DISABLED" + register "gpio1_output_enable" = "true" + register "gpio1_src_select" = "GPIO1_SRC_GPIO" + register "gpio2_src_select" = "GPIO2_SRC_HIGH_IMPEDANCE" + device i2c 0x43 on end end end #I2C0 device ref i2c1 on -- To view, visit https://review.coreboot.org/c/coreboot/+/60331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c Gerrit-Change-Number: 60331 Gerrit-PatchSet: 40 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Name of user not set #1004174 Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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