coreboot-gerrit March 2022

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Change in coreboot[master]: mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED
by Raul Rangel (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62923 ) Change subject: mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932 Gerrit-Change-Number: 62923 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 18 Mar 2022 16:08:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Build APCB sources into amdfw when present
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62877 ) Change subject: mb/google/skyrim: Build APCB sources into amdfw when present ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > i don't like this approach too much, since this basically hard-codes the mainboard-specific file nam […] oh, sorry for the confusion, this is in skyrim's makefile, so it's all good -- To view, visit https://review.coreboot.org/c/coreboot/+/62877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71b30a5716f2e0d60d07a0ec29f98609c1f2a8b7 Gerrit-Change-Number: 62877 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Fri, 18 Mar 2022 16:08:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add UfsEnable parameter
by Eric Lai (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Tim Wawrzynczak, Meera Ravindranath. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62914 ) Change subject: soc/intel/alderlake: Add UfsEnable parameter ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: This is define in eltherlake #define PCH_DEV_UFS0 _PCH_DEV(SIO0, 5) #define PCH_DEV_UFS1 _PCH_DEV(SIO0, 7) Icelake use 5 #define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5) Alderlake use 7 #define PCH_DEVFN_UFS _PCH_DEVFN(ISH, 7) probably it could be port2 here hmm.... -- To view, visit https://review.coreboot.org/c/coreboot/+/62914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9b956204fb1001977d86c0d898b2734efb32271 Gerrit-Change-Number: 62914 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 16:04:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED
by Fred Reitberger (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62923 ) Change subject: mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932 Gerrit-Change-Number: 62923 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 18 Mar 2022 16:03:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Build APCB sources into amdfw when present
by Raul Rangel (Code Review) 18 Mar '22

18 Mar '22

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62877 ) Change subject: mb/google/skyrim: Build APCB sources into amdfw when present ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > i don't like this approach too much, since this basically hard-codes the mainboard-specific file nam […] How does this impact the Chausie? -- To view, visit https://review.coreboot.org/c/coreboot/+/62877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71b30a5716f2e0d60d07a0ec29f98609c1f2a8b7 Gerrit-Change-Number: 62877 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Fri, 18 Mar 2022 16:02:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile: Add .SECONDARY
by Raul Rangel (Code Review) 18 Mar '22

18 Mar '22

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62398 ) Change subject: Makefile: Add .SECONDARY ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62398/comment/57433ed6_f58b2bc7 PS2, Line 10: Setting .SECONDARY will prevent make from : deleting the files. > Hah, thanks, that does the job! :) Thanks for testing: CB:62922 -- To view, visit https://review.coreboot.org/c/coreboot/+/62398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657a696acc71d42ba94442d4754ee63efd3e6a74 Gerrit-Change-Number: 62398 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 18 Mar 2022 16:01:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim/devicetree: set PSPP policy to DXIO_PSPP_DISABLED
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62924 ) Change subject: mb/google/skyrim/devicetree: set PSPP policy to DXIO_PSPP_DISABLED ...................................................................... mb/google/skyrim/devicetree: set PSPP policy to DXIO_PSPP_DISABLED Right now, the PSPP policy that controls if the PCIe lanes can be dynamically downgraded to a lower speed to save some power needs to be disabled in order for the link training to be successful. Once this feature is working, PSPP will be reenabled. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af --- M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/62924/1 diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 7d4fb7f..03bb55e 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -47,6 +47,8 @@ register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works + device domain 0 on device ref lpc_bridge on chip ec/google/chromeec -- To view, visit https://review.coreboot.org/c/coreboot/+/62924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af Gerrit-Change-Number: 62924 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62923 ) Change subject: mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED ...................................................................... mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED Right now, the PSPP policy that controls if the PCIe lanes can be dynamically downgraded to a lower speed to save some power needs to be disabled in order for the link training to be successful. Once this feature is working, the PSPP policy will be switched to balanced again. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932 --- M src/mainboard/amd/chausie/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/62923/1 diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index f3a84f3..7f37be2 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -24,7 +24,7 @@ register "s0ix_enable" = "true" - register "pspp_policy" = "DXIO_PSPP_BALANCED" + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works device domain 0 on device ref iommu on end -- To view, visit https://review.coreboot.org/c/coreboot/+/62923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932 Gerrit-Change-Number: 62923 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile.inc: Explicitly delete coreboot.pre
by Raul Rangel (Code Review) 18 Mar '22

18 Mar '22

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62922 ) Change subject: Makefile.inc: Explicitly delete coreboot.pre ...................................................................... Makefile.inc: Explicitly delete coreboot.pre coreboot.pre doesn't follow the standard Make conventions. It gets modified by multiple rules, and thus we can't compute the dependencies correctly. This means we need to manually delete it before starting the dependency calculations. Fixes: dd6efce934f ("Makefile: Add .SECONDARY") Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: If5fa3f0b8d314369a044658e452bd75bc7709397 --- M Makefile.inc 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/62922/1 diff --git a/Makefile.inc b/Makefile.inc index ec2d097..279f8d4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1115,6 +1115,10 @@ TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE) endif +# coreboot.pre doesn't follow the standard Make conventions. It gets modified +# by multiple rules, and thus we can't compute the dependencies correctly. +$(shell rm -f $(obj)/coreboot.pre) + ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) -- To view, visit https://review.coreboot.org/c/coreboot/+/62922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5fa3f0b8d314369a044658e452bd75bc7709397 Gerrit-Change-Number: 62922 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/skyrim: Build APCB sources into amdfw when present
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62877 ) Change subject: mb/google/skyrim: Build APCB sources into amdfw when present ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: i don't like this approach too much, since this basically hard-codes the mainboard-specific file name on soc level and for example chausie uses different file names -- To view, visit https://review.coreboot.org/c/coreboot/+/62877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71b30a5716f2e0d60d07a0ec29f98609c1f2a8b7 Gerrit-Change-Number: 62877 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Fri, 18 Mar 2022 15:53:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2022