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Change in coreboot[master]: drivers/i2c/cs35l53: Add driver for generating device in SSDT
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61448 ) Change subject: drivers/i2c/cs35l53: Add driver for generating device in SSDT ...................................................................... drivers/i2c/cs35l53: Add driver for generating device in SSDT This patch is adding support for Cirrus Logic CS35l41/CS35l53 smart amplifier. This part is now used in number of new chromebook's HW designs by several vendors. This driver uses the ACPI Device Property interface to generate the required parameters into the _DSD table format expected by the kernel. For detailed information about these properties, please check Linux kernel documentation: /Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml Change-Id: I2cbb1cef89f8d56ee73fab06c68933a2ab8c3606 Signed-off-by: Stefan Binding <sbinding(a)opensource.cirrus.com> Signed-off-by: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61448 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/drivers/i2c/cs35l53/Kconfig A src/drivers/i2c/cs35l53/Makefile.inc A src/drivers/i2c/cs35l53/chip.h A src/drivers/i2c/cs35l53/cs35l53.c 4 files changed, 300 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/i2c/cs35l53/Kconfig b/src/drivers/i2c/cs35l53/Kconfig new file mode 100644 index 0000000..38d6617 --- /dev/null +++ b/src/drivers/i2c/cs35l53/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_I2C_CS35L53 + bool + depends on HAVE_ACPI_TABLES diff --git a/src/drivers/i2c/cs35l53/Makefile.inc b/src/drivers/i2c/cs35l53/Makefile.inc new file mode 100644 index 0000000..21a749f --- /dev/null +++ b/src/drivers/i2c/cs35l53/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_CS35L53) += cs35l53.c diff --git a/src/drivers/i2c/cs35l53/chip.h b/src/drivers/i2c/cs35l53/chip.h new file mode 100644 index 0000000..9aeb874 --- /dev/null +++ b/src/drivers/i2c/cs35l53/chip.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_device.h> + +#define CS35L53_MAX_GPIOS 2 + +enum cs35l53_boost_type { + INTERNAL_BOOST = 0, + EXTERNAL_BOOST = 1, +}; + +enum cs35l53_boost_ind_nanohenrys { + BOOST_IND_1000_NH = 1000, + BOOST_IND_1200_NH = 1200, + BOOST_IND_1500_NH = 1500, + BOOST_IND_2200_NH = 2200, +}; + +enum cs35l53_asp_sdout_hiz { + ASP_SDOUT_LOGIC0_UNUSED_LOGIC0_DISABLED = 0, + ASP_SDOUT_HIZ_UNUSED_LOGIC0_DISABLED = 1, + ASP_SDOUT_LOGIC0_UNUSED_HIZ_DISABLED = 2, + ASP_SDOUT_HIZ_UNUSED_HIZ_DISABLED = 3, +}; + +enum cs35l53_gpio1_src { + GPIO1_SRC_HIGH_IMPEDANCE = 0, + GPIO1_SRC_GPIO = 1, + GPIO1_SRC_SYNC = 2, + GPIO1_SRC_MCLK_INPUT = 3, +}; + +enum cs35l53_gpio2_src { + GPIO2_SRC_HIGH_IMPEDANCE = 0, + GPIO2_SRC_GPIO = 1, + GPIO2_SRC_OPEN_DRAIN = 2, + GPIO2_SRC_MCLK_INPUT = 3, + GPIO2_SRC_PUSH_PULL_INTB = 4, + GPIO2_SRC_PUSH_PULL_INT = 5, +}; + +/* + * Cirrus Logic CS35L53 Audio Codec devicetree bindings + * linux/Documentation/devicetree/bindings/sound/cirrus,cs35l53.yaml + */ +struct drivers_i2c_cs35l53_config { + const char *name; /* ACPI Device Name */ + + const char *sub; /* SUB ID to uniquely identify system */ + + /* Interrupt configuration */ + struct acpi_irq irq; + + /* Use GPIO based interrupt instead of PIRQ */ + struct acpi_gpio irq_gpio; + + /* Use GPIO based reset gpio */ + struct acpi_gpio reset_gpio; + + /* I2C Bus Frequency in Hertz (default 400kHz) */ + unsigned int bus_speed; + + /* Define cs35l53 parameters */ + /* + * cirrus,boost-type : Configures the type of Boost being used. + * Internal boost requires boost-peak-milliamp, boost-ind-nanohenry and + * boost-cap-microfarad. + * External Boost must have GPIO1 as GPIO output. GPIO1 will be set high to + * enable boost voltage. + */ + enum cs35l53_boost_type boost_type; + + /* + * cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA. + * Configures the peak current by monitoring the current through the boost FET. + * Range starts at 1600 mA and goes to a maximum of 4500 mA with increments + * of 50 mA. See section 4.3.6 of the datasheet for details. + */ + unsigned int boost_peak_milliamp; + + /* + * cirrus,boost-ind-nanohenry : Boost inductor value, expressed in nH. Valid + * values include 1000, 1200, 1500 and 2200. + */ + enum cs35l53_boost_ind_nanohenrys boost_ind_nanohenry; + + /* + * cirrus,boost-cap-microfarad : Total equivalent boost capacitance on the VBST + * and VAMP pins, derated at 11 volts DC. The value must be rounded to the + * nearest integer and expressed in uF. + */ + unsigned int boost_cap_microfarad; + + /* + * cirrus,asp-sdout-hiz : Audio serial port SDOUT Hi-Z control. Sets the Hi-Z + * configuration for SDOUT pin of amplifier. + * 0 = Logic 0 during unused slots, and while all transmit channels disabled + * 1 = Hi-Z during unused slots but logic 0 while all transmit channels disabled + * 2 = Logic 0 during unused slots, but Hi-Z while all transmit channels disabled + * 3 = Hi-Z during unused slots and while all transmit channels disabled + */ + enum cs35l53_asp_sdout_hiz asp_sdout_hiz; + + /* + * cirrus,gpio1-polarity-invert : Boolean which specifies whether the GPIO1 + * level is inverted. + */ + bool gpio1_polarity_invert; + + /* + * cirrus,gpio2-polarity-invert : Boolean which specifies whether the GPIO2 + * level is inverted. + */ + bool gpio2_polarity_invert; + + /* + * cirrus,gpio1-output-enable : Boolean which specifies whether the GPIO1 pin + * is configured as an output. + */ + bool gpio1_output_enable; + + /* + * cirrus,gpio2-output-enable : Boolean which specifies whether the GPIO2 pin + * is configured as an output. + */ + bool gpio2_output_enable; + + /* + * cirrus,gpio1-src-select : Configures the function of the GPIO1 pin. + * GPIO1: + * 0 = High Impedance (Default) + * 1 = GPIO + * 2 = Sync + * 3 = MCLK input + */ + enum cs35l53_gpio1_src gpio1_src_select; + + /* + * cirrus,gpio2-src-select : Configures the function of the GPIO2 pin. + * GPIO2: + * 0 = High Impedance (Default) + * 1 = GPIO + * 2 = Open Drain INTB + * 3 = MCLK input + * 4 = Push-pull INTB (active low) + * 5 = Push-pull INT (active high) + */ + enum cs35l53_gpio2_src gpio2_src_select; +}; diff --git a/src/drivers/i2c/cs35l53/cs35l53.c b/src/drivers/i2c/cs35l53/cs35l53.c new file mode 100644 index 0000000..1909bef --- /dev/null +++ b/src/drivers/i2c/cs35l53/cs35l53.c @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> +#include <console/console.h> +#include <device/i2c_simple.h> +#include <device/device.h> +#include <device/path.h> + +#include "chip.h" + +#define CS35L53_ACPI_HID "CSC3541" + +static void cs35l53_fill_ssdt(const struct device *dev) +{ + struct drivers_i2c_cs35l53_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + const char *path = acpi_device_path(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dsd; + int gpio_index = 0; + + if (!scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", CS35L53_ACPI_HID); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_name_string("_SUB", config->sub); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + /* Use either Interrupt() or GpioInt() */ + if (config->irq_gpio.pin_count) + acpi_device_write_gpio(&config->irq_gpio); + else + acpi_device_write_interrupt(&config->irq); + + /* for cs35l53 reset gpio */ + if (config->reset_gpio.pin_count) + acpi_device_write_gpio(&config->reset_gpio); + + acpigen_write_resourcetemplate_footer(); + + /* Add Child Device Properties */ + dsd = acpi_dp_new_table("_DSD"); + if (config->irq_gpio.pin_count) + acpi_dp_add_gpio(dsd, "irq-gpios", path, + gpio_index++, /* Index = 0 */ + 0, /* Pin = 0 (There is a single pin in the GPIO resource). */ + config->irq_gpio.active_low); + if (config->reset_gpio.pin_count) + acpi_dp_add_gpio(dsd, "reset-gpios", path, + gpio_index++, /* Index = 0 or 1 (if irq gpio is written). */ + 0, /* Pin = 0 (There is a single pin in the GPIO resource). */ + config->reset_gpio.active_low); + + acpi_dp_add_integer(dsd, "cirrus,boost-type", config->boost_type); + + switch (config->boost_type) { + case INTERNAL_BOOST: + if ((config->boost_peak_milliamp > 4500) || + (config->boost_peak_milliamp < 1600) || + (config->boost_peak_milliamp % 50)) { + printk(BIOS_ERR, + "%s: Incorrect boost_peak_milliamp(%d). Using default of 4500 mA\n", + __func__, config->boost_peak_milliamp); + config->boost_peak_milliamp = 4500; + } + acpi_dp_add_integer(dsd, "cirrus,boost-peak-milliamp", + config->boost_peak_milliamp); + acpi_dp_add_integer(dsd, "cirrus,boost-ind-nanohenry", + config->boost_ind_nanohenry); + acpi_dp_add_integer(dsd, "cirrus,boost-cap-microfarad", + config->boost_cap_microfarad); + break; + case EXTERNAL_BOOST: + config->gpio1_output_enable = true; + config->gpio1_src_select = GPIO1_SRC_GPIO; + break; + default: + break; + } + + acpi_dp_add_integer(dsd, "cirrus,asp-sdout-hiz", config->asp_sdout_hiz); + acpi_dp_add_integer(dsd, "cirrus,gpio1-polarity-invert", + config->gpio1_polarity_invert); + acpi_dp_add_integer(dsd, "cirrus,gpio1-output-enable", + config->gpio1_output_enable); + acpi_dp_add_integer(dsd, "cirrus,gpio1-src-select", config->gpio1_src_select); + acpi_dp_add_integer(dsd, "cirrus,gpio2-polarity-invert", + config->gpio2_polarity_invert); + acpi_dp_add_integer(dsd, "cirrus,gpio2-output-enable", + config->gpio2_output_enable); + acpi_dp_add_integer(dsd, "cirrus,gpio2-src-select", config->gpio2_src_select); + + /* Write Device Property Hierarchy */ + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s address 0%xh irq %d\n", + acpi_device_path(dev), dev->chip_ops->name, + dev->path.i2c.device, config->irq.pin); +} + +static const char *cs35l53_acpi_name(const struct device *dev) +{ + struct drivers_i2c_cs35l53_config *config = dev->chip_info; + static char name[ACPI_NAME_BUFFER_SIZE]; + + if (config->name) + return config->name; + + snprintf(name, sizeof(name), "D%03.3X", dev->path.i2c.device); + return name; +} + +static struct device_operations cs35l53_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = cs35l53_acpi_name, + .acpi_fill_ssdt = cs35l53_fill_ssdt, +}; + +static void cs35l53_enable(struct device *dev) +{ + dev->ops = &cs35l53_ops; +} + +struct chip_operations drivers_i2c_cs35l53_ops = { + CHIP_NAME("Cirrus Logic CS35L53 Audio Codec") + .enable_dev = cs35l53_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/61448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cbb1cef89f8d56ee73fab06c68933a2ab8c3606 Gerrit-Change-Number: 61448 Gerrit-PatchSet: 12 Gerrit-Owner: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Name of user not set #1004174 Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Vitaly Rodionov <vitaly.rodionov(a)gmail.com> Gerrit-CC: Xiang Liu <xiang.liu(a)cirrus.corp-partner.google.com> Gerrit-CC: YH Lin <yueherngl(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: commonlib/bsd/helpers: Move STIRNGIFY() from string.h
by Jakub Czapiga (Code Review) 18 Mar '22

18 Mar '22

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62921 ) Change subject: commonlib/bsd/helpers: Move STIRNGIFY() from string.h ...................................................................... commonlib/bsd/helpers: Move STIRNGIFY() from string.h STRINGIFY() macro should be accessible to util programs as well, to make it usable in commonlib headers. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c --- M src/commonlib/bsd/include/commonlib/bsd/helpers.h M src/include/string.h 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/62921/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/helpers.h b/src/commonlib/bsd/include/commonlib/bsd/helpers.h index 733b05a..4995305 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/helpers.h +++ b/src/commonlib/bsd/include/commonlib/bsd/helpers.h @@ -126,4 +126,10 @@ #define retry(attempts, condition, ...) \ _retry_impl(attempts, condition, __VA_ARGS__) +/* Stringify a token */ +#ifndef STRINGIFY +#define _STRINGIFY(x) #x +#define STRINGIFY(x) _STRINGIFY(x) +#endif + #endif /* COMMONLIB_BSD_HELPERS_H */ diff --git a/src/include/string.h b/src/include/string.h index 3cfa18d..f595c7e 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -7,12 +7,6 @@ #include <stddef.h> #include <stdio.h> -/* Stringify a token */ -#ifndef STRINGIFY -#define _STRINGIFY(x) #x -#define STRINGIFY(x) _STRINGIFY(x) -#endif - void *memcpy(void *dest, const void *src, size_t n); void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); -- To view, visit https://review.coreboot.org/c/coreboot/+/62921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c Gerrit-Change-Number: 62921 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: commonlib/timestamp_serialized: Add timestamp enum to name mapping
by Jakub Czapiga (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Jakub Czapiga, Tim Wawrzynczak. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62709 to look at the new patch set (#6). Change subject: commonlib/timestamp_serialized: Add timestamp enum to name mapping ...................................................................... commonlib/timestamp_serialized: Add timestamp enum to name mapping Some solutions require readable form of timestamps, which does not contain spaces. Current descriptive timestamp names do not meet this criteria. Also, mapping enums to their text representation allows for quick grepping (use of grep command) to find relevant timestamps in the code. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ifd49f20d6b00a5bbd21804cea3a50b8cef074cd1 --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 139 insertions(+), 132 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/62709/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/62709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd49f20d6b00a5bbd21804cea3a50b8cef074cd1 Gerrit-Change-Number: 62709 Gerrit-PatchSet: 6 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/skyrim: Build APCB sources into amdfw when present
by Karthik Ramasubramanian (Code Review) 18 Mar '22

18 Mar '22

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62877 ) Change subject: mb/google/skyrim: Build APCB sources into amdfw when present ...................................................................... mb/google/skyrim: Build APCB sources into amdfw when present BUG=b:224618411 TEST=util/abuild/abuild -t GOOGLE_SKYRIM with and without APCB Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I71b30a5716f2e0d60d07a0ec29f98609c1f2a8b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62877 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/skyrim/Makefile.inc 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/Makefile.inc b/src/mainboard/google/skyrim/Makefile.inc index 94708ac..e66f7c9 100644 --- a/src/mainboard/google/skyrim/Makefile.inc +++ b/src/mainboard/google/skyrim/Makefile.inc @@ -13,3 +13,11 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_SBR_D5.bin),) +$(info APCB sources present.) +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_SBR_D5.bin +APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_SBR_D5.bin +else +$(info APCB sources not found. Skipping APCB.) +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/62877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71b30a5716f2e0d60d07a0ec29f98609c1f2a8b7 Gerrit-Change-Number: 62877 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Fix I2C voltages
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62874 ) Change subject: mb/google/skyrim: Fix I2C voltages ...................................................................... mb/google/skyrim: Fix I2C voltages Needed so i2c communication works. BUG=b:224618411 TEST=build skyrim Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I8ec7c18cae509b5683cb73153fd6d3747cf9d753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62874 Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Jon Murphy: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 61bc93d..7d4fb7f 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -41,6 +41,12 @@ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" + # I2C Pad Control RX Select Configuration + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" # Touchpad + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" # Touchscreen + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC + device domain 0 on device ref lpc_bridge on chip ec/google/chromeec -- To view, visit https://review.coreboot.org/c/coreboot/+/62874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ec7c18cae509b5683cb73153fd6d3747cf9d753 Gerrit-Change-Number: 62874 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Enable tis_plat_irq_status
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62873 ) Change subject: mb/google/skyrim: Enable tis_plat_irq_status ...................................................................... mb/google/skyrim: Enable tis_plat_irq_status This will fix: > [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50! BUG=b:224618411 TEST=Compile skyrim Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5add694506ad089adcc8961f101bf507bc39a522 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62873 Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skyrim/variants/baseboard/Makefile.inc M src/mainboard/google/skyrim/variants/baseboard/gpio.c A src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c 3 files changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Jon Murphy: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc b/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc index dc1c1fe..7706e50 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc @@ -1,7 +1,11 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += tpm_tis.c ramstage-y += gpio.c +ramstage-y += tpm_tis.c + +verstage-y += tpm_tis.c smm-y += gpio.c diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index f095651..204ddf6 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -39,7 +39,7 @@ /* SOC_SAR_INT_L */ PAD_SCI(GPIO_17, PULL_NONE, EDGE_LOW), /* GSC_SOC_INT_L */ - PAD_GPI(GPIO_18, PULL_NONE), + PAD_INT(GPIO_18, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* I2C3_SCL */ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* I2C3_SDA */ diff --git a/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c b/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c new file mode 100644 index 0000000..0102baa --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <security/tpm/tis.h> +#include <soc/gpio.h> + +int tis_plat_irq_status(void) +{ + return gpio_interrupt_status(GPIO_18); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5add694506ad089adcc8961f101bf507bc39a522 Gerrit-Change-Number: 62873 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Add DXIO descriptors
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

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Change in coreboot[master]: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
by Ben Chuang (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Kevin Chang, Paul Menzel. Ben Chuang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62917 ) Change subject: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62917/comment/eb0599c0_7767c8f4 PS2, Line 10: Linux > Please mention the version. Done https://review.coreboot.org/c/coreboot/+/62917/comment/c40bc132_8efdd9e3 PS2, Line 9: Add an option to set L1 entry delay to Max for GL9763E. The L1 entry delay will : be changed to expected value by sdhci-pci-gli driver in Linux. > Please use 72 characters per line. Done https://review.coreboot.org/c/coreboot/+/62917/comment/75776a42_e968c08c PS2, Line 13: TEST=Verify GL9763 L1 entry delay is Max in coreboot > How? Modified. -- To view, visit https://review.coreboot.org/c/coreboot/+/62917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601 Gerrit-Change-Number: 62917 Gerrit-PatchSet: 3 Gerrit-Owner: Ben Chuang <benchuanggli(a)gmail.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lai Jason <jasonlai.genesyslogic(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 18 Mar 2022 15:03:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Add DXIO descriptors
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62903 ) Change subject: mb/google/skyrim: Add DXIO descriptors ...................................................................... Patch Set 8: (10 comments) Patchset: PS8: sorry for the confusion created here; had to figure out things myself first File src/mainboard/google/skyrim/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/62903/comment/c755eb11_bf5d3b32 PS8, Line 12: 0 1 https://review.coreboot.org/c/coreboot/+/62903/comment/a1a31368_7e768a7a PS8, Line 13: 0 1 https://review.coreboot.org/c/coreboot/+/62903/comment/97e18a54_7b58837b PS8, Line 24: 1 0 https://review.coreboot.org/c/coreboot/+/62903/comment/99454e9b_a3c38eec PS8, Line 25: 1 0 https://review.coreboot.org/c/coreboot/+/62903/comment/162a75ec_2fea141a PS8, Line 38: .start_logical_lane = 2, : .end_logical_lane = 3, not sure if the numbers need to be swapped or not https://review.coreboot.org/c/coreboot/+/62903/comment/f9608fa5_e0a4b28d PS8, Line 49: {/* unused MXM */ : .engine_type = UNUSED_ENGINE, : .port_present = false, : .start_logical_lane = 4, : .end_logical_lane = 7, : .device_number = 0, : .function_number = 0, : .link_speed_capability = GEN3, : .turn_off_unused_lanes = true, : }, : { /* unused MXM2 */ : .engine_type = UNUSED_ENGINE, : .port_present = false, : .start_logical_lane = 8, : .end_logical_lane = 11, : .device_number = 0, : .function_number = 0, : .link_speed_capability = GEN3, : .turn_off_unused_lanes = true, : }, : { /* unused MXM3 */ : .engine_type = UNUSED_ENGINE, : .port_present = false, : .start_logical_lane = 12, : .end_logical_lane = 15, : .device_number = 0, : .function_number = 0, : .link_speed_capability = GEN3, : .turn_off_unused_lanes = true, : }, : { /* unused SSD2 */ : .engine_type = UNUSED_ENGINE, : .port_present = false, : .start_logical_lane = 16, : .end_logical_lane = 19, : .device_number = 0, : .function_number = 0, : .link_speed_capability = GEN3, : .turn_off_unused_lanes = true, : }, can this be removed? https://review.coreboot.org/c/coreboot/+/62903/comment/3a6003bd_3e38f297 PS8, Line 98: DDI_HDMI DDI_DP File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62903/comment/2d844b00_9f9f10cb PS8, Line 50: device ref gpp_bridge_0 on # WLAN : chip drivers/wifi/generic : register "wake" = "GEVENT_8" : device pci 00.0 on end : end : end : device ref gpp_bridge_1 on end # SD wifi before sd turned out to be the correct order after figuring out how the physical to logical lane numbering works on this soc File src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/62903/comment/b53cdfb5_ef613c36 PS8, Line 9: : #define SD_DEVFN PCIE_GPP_2_0_DEVFN : #define WLAN_DEVFN PCIE_GPP_2_1_DEVFN swap -- To view, visit https://review.coreboot.org/c/coreboot/+/62903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 Gerrit-Change-Number: 62903 Gerrit-PatchSet: 8 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 15:03:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add UfsEnable parameter
by Tim Wawrzynczak (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Eric Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62914 ) Change subject: soc/intel/alderlake: Add UfsEnable parameter ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: also there is https://review.coreboot.org/c/coreboot/+/62856 -- To view, visit https://review.coreboot.org/c/coreboot/+/62914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9b956204fb1001977d86c0d898b2734efb32271 Gerrit-Change-Number: 62914 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 14:57:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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