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Change subject: soc/intel/adl: Remove IOM Mctp command from TCSS ASL
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62861/comment/5fdd1782_fe4379e2
PS2, Line 12: Recently as part of s0ix hang issue
> Where did it hang exactly?
S0ix entry or exit
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 )
Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62919/comment/3192c99d_6861e753
PS2, Line 9: didn't
doesn’t
https://review.coreboot.org/c/coreboot/+/62919/comment/c2de4fe7_306d997e
PS2, Line 9: disable
Missing third person s? disables
https://review.coreboot.org/c/coreboot/+/62919/comment/86b7faf3_d4d6b121
PS2, Line 12: TEST=Build FW and run stress exceed 2500 cycles.
Did it fail before? If yes, please mention that at the beginning of the commit message.
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Change subject: mb/google/brya/var/taeko: Enable Genesys L1 entry delay
......................................................................
Removed Code-Review+2 by Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com>
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Change subject: mb/google/brya/var/taeko: Enable Genesys L1 entry delay
......................................................................
Patch Set 3: Code-Review+2
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Kevin Chang has uploaded a new patch set (#2) to the change originally created by Ben Chuang. ( https://review.coreboot.org/c/coreboot/+/62917 )
Change subject: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
......................................................................
drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
Add an option to set L1 entry delay to Max for GL9763E. The L1 entry delay will
be changed to expected value by sdhci-pci-gli driver in Linux.
BUG=b:220079865
TEST=Verify GL9763 L1 entry delay is Max in coreboot
Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601
Signed-off-by: Ben Chuang <benchuanggli(a)gmail.com>
---
M src/drivers/genesyslogic/gl9763e/Kconfig
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/genesyslogic/gl9763e/gl9763e.h
3 files changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/62917/2
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62771
to look at the new patch set (#7).
Change subject: mb/google/brya/vell: Move WWAN devices for vell
......................................................................
mb/google/brya/vell: Move WWAN devices for vell
This was to merge PCIe ACPI code to WWAN device. Also, RTD3 devices are
add to overridetree.cb where WWAN is present for vell.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b
---
M src/mainboard/google/brya/variants/vell/overridetree.cb
1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62771/7
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