coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/guybrush/port_descriptors: use enum values for link speed
by Raul Rangel (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62908 ) Change subject: mb/google/guybrush/port_descriptors: use enum values for link speed ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dddc57e05ec2395ca980bb63320bb9ee5242c29 Gerrit-Change-Number: 62908 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 18 Mar 2022 15:51:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add UfsEnable parameter
by Eric Lai (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62914 ) Change subject: soc/intel/alderlake: Add UfsEnable parameter ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > also there is https://review.coreboot. […] interesting, who is correct? b/c I think 0 is correct for the port 1. -- To view, visit https://review.coreboot.org/c/coreboot/+/62914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9b956204fb1001977d86c0d898b2734efb32271 Gerrit-Change-Number: 62914 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 18 Mar 2022 15:51:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Send EOP early in the boot sequence
by Michael Niewöhner (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Maulik V Vaghela. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62272 ) Change subject: soc/intel/adl: Send EOP early in the boot sequence ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/62272/comment/983874c0_c8847e10 PS11, Line 158: Intel CSE team recommends to send EOP close to FW init (between FSP-S exit and : * current boot sequence) to reduce message response time from CSE hence moving : * sending EOP to earlier stage. > The reason we are doing this is we have performance metrics to meet, and if you wait "too long", the […] Sure, I got this - but why is that only relevant on alderlake? -- To view, visit https://review.coreboot.org/c/coreboot/+/62272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Gerrit-Change-Number: 62272 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 15:50:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile: Add .SECONDARY
by Michael Niewöhner (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Raul Rangel. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62398 ) Change subject: Makefile: Add .SECONDARY ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62398/comment/59a554cc_0f61d4d9 PS2, Line 10: Setting .SECONDARY will prevent make from : deleting the files. > Can you try this out? […] Hah, thanks, that does the job! :) -- To view, visit https://review.coreboot.org/c/coreboot/+/62398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657a696acc71d42ba94442d4754ee63efd3e6a74 Gerrit-Change-Number: 62398 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Fri, 18 Mar 2022 15:49:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/port_descriptors: use enum values for link speed
by Karthik Ramasubramanian (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Raul Rangel, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62908 ) Change subject: mb/google/guybrush/port_descriptors: use enum values for link speed ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Thanks. Improves readability. -- To view, visit https://review.coreboot.org/c/coreboot/+/62908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dddc57e05ec2395ca980bb63320bb9ee5242c29 Gerrit-Change-Number: 62908 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 18 Mar 2022 15:48:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller
by Subrata Banik (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Meera Ravindranath. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62856 ) Change subject: soc/intel/alderlake: Add support for UFS controller ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/62856/comment/281bc1e6_a2a08627 PS1, Line 619: s_cfg->UfsEnable[1] = 0; > As I commented on CB:62662 I don't understand whyt this is array and why we're using index 1 here. > > Comments on FspsUpd.h seems wrong not helping anything. https://review.coreboot.org/c/coreboot/+/62914/1..2/src/soc/intel/alderlake… It's an adjustment made in FSP to compliment many platform IMO. I don't think we need to disable index 0 and enable 1 (unless you know the exact assumption inside FSP). (I guess you have carried away with FSP default UPD value assignment which enforces index 0 to set disable. is it ?) Also in EDS PMC offset 0x1E44 bit 8-7 marked as reserved hence, unable to understand what is the exact check that FSP does. -- To view, visit https://review.coreboot.org/c/coreboot/+/62856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 Gerrit-Change-Number: 62856 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 15:44:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable UFS for ADL-N RVP
by Subrata Banik (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Kangheui Won, Rizwan Qureshi, Tim Wawrzynczak, Meera Ravindranath, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62662 ) Change subject: mb/intel/adlrvp: Enable UFS for ADL-N RVP ...................................................................... Patch Set 3: (1 comment) File src/mainboard/intel/adlrvp/devicetree_n.cb: https://review.coreboot.org/c/coreboot/+/62662/comment/6a208b6d_eeb2846f PS3, Line 283: on then how pcie_rp7 is working here https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/ch… when pcie_rp1 is off? device pci 1c.0 alias pcie_rp1 off end FSP should have migrate this PCI device config space under func 0 using swaping isn't it? -- To view, visit https://review.coreboot.org/c/coreboot/+/62662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1 Gerrit-Change-Number: 62662 Gerrit-PatchSet: 3 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 18 Mar 2022 15:44:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Disable unused spm_thermal
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62890 ) Change subject: soc/mediatek/mt8186: Disable unused spm_thermal ...................................................................... soc/mediatek/mt8186: Disable unused spm_thermal In MT8186, we need to disable spm_thermal to prevent it from influencing other wdt status. There are two hardware pathes which are used for asserting watchdog from thermal. We can disable status of path 1 because status of path 2 is used. 1. Thermal -> SPM -> WDT 2. Thermal -> WDT Spm_thermal (path 1) is a flexible option for software control, and the hardware designer suggests that we should disable it if we don't use it. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I0ffde6bad3000a64e3b5782edaa72c62da034302 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62890 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/wdt.h M src/soc/mediatek/mt8186/bootblock.c M src/soc/mediatek/mt8186/wdt.c 3 files changed, 15 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h index cd43134..ebf7f49 100644 --- a/src/soc/mediatek/common/include/soc/wdt.h +++ b/src/soc/mediatek/common/include/soc/wdt.h @@ -14,7 +14,9 @@ u32 wdt_interval; u32 wdt_swrst; u32 wdt_swsysrst; - u32 reserved[9]; + u32 reserved0[5]; + u32 wdt_req_mode; + u32 reserved1[3]; u32 wdt_debug_ctrl; }; @@ -38,6 +40,7 @@ static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE; +void mtk_wdt_preinit(void); int mtk_wdt_init(void); void mtk_wdt_clr_status(void); diff --git a/src/soc/mediatek/mt8186/bootblock.c b/src/soc/mediatek/mt8186/bootblock.c index e5d1e73..29de7fb 100644 --- a/src/soc/mediatek/mt8186/bootblock.c +++ b/src/soc/mediatek/mt8186/bootblock.c @@ -12,6 +12,7 @@ { mtk_mmu_init(); bustracker_init(); + mtk_wdt_preinit(); mtk_wdt_init(); mt_pll_init(); unmask_eint_event_mask(); diff --git a/src/soc/mediatek/mt8186/wdt.c b/src/soc/mediatek/mt8186/wdt.c index fbc9bb9..f9e0d8a 100644 --- a/src/soc/mediatek/mt8186/wdt.c +++ b/src/soc/mediatek/mt8186/wdt.c @@ -10,8 +10,18 @@ #include <soc/wdt.h> #define MTK_WDT_CLR_STATUS_VAL 0x22 +#define MTK_WDT_REQ_MOD_KEY_VAL 0x33 DEFINE_BITFIELD(MTK_WDT_CLR_STATUS, 31, 24) +DEFINE_BITFIELD(MTK_WDT_REQ_MOD_KEY, 31, 24) +DEFINE_BIT(MTK_WDT_SPM_THERMAL_EN, 0) + +void mtk_wdt_preinit(void) +{ + SET32_BITFIELDS(&mtk_wdt->wdt_req_mode, + MTK_WDT_SPM_THERMAL_EN, 0, + MTK_WDT_REQ_MOD_KEY, MTK_WDT_REQ_MOD_KEY_VAL); +} void mtk_wdt_clr_status(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/62890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ffde6bad3000a64e3b5782edaa72c62da034302 Gerrit-Change-Number: 62890 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: Trigger wdt SW reset when wdt status is not equal to 0
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62797 ) Change subject: soc/mediatek: Trigger wdt SW reset when wdt status is not equal to 0 ...................................................................... soc/mediatek: Trigger wdt SW reset when wdt status is not equal to 0 Because we close external signal in kernel driver since MT8195, it's more reasonable to trigger sw reset with exteranl signal again whenever the wdt status is not equal to 0. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ic6128df7eadaebcf7ff8d4c5492e3e0cfbab6e36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62797 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/wdt.c 1 file changed, 13 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 108648f..d58ac32 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -40,18 +40,21 @@ printk(BIOS_INFO, "WDT: Status = %#x\n", wdt_sta); printk(BIOS_INFO, "WDT: Last reset was "); - if (wdt_sta & MTK_WDT_STA_HW_RST) { - printk(BIOS_INFO, "hardware watchdog\n"); + if (!wdt_sta) { + printk(BIOS_INFO, "cold boot\n"); + } else { + if (wdt_sta & MTK_WDT_STA_HW_RST) + printk(BIOS_INFO, "hardware watchdog\n"); + else if (wdt_sta & MTK_WDT_STA_SW_RST) + printk(BIOS_INFO, "normal software reboot\n"); + else if (wdt_sta & MTK_WDT_STA_SPM_RST) + printk(BIOS_INFO, "SPM reboot\n"); + else + printk(BIOS_INFO, "other reset type: %#.8x\n", wdt_sta); + mark_watchdog_tombstone(); mtk_wdt_swreset(); - } else if (wdt_sta & MTK_WDT_STA_SW_RST) - printk(BIOS_INFO, "normal software reboot\n"); - else if (wdt_sta & MTK_WDT_STA_SPM_RST) - printk(BIOS_INFO, "SPM reboot\n"); - else if (!wdt_sta) - printk(BIOS_INFO, "cold boot\n"); - else - printk(BIOS_INFO, "unexpected reset type: %#.8x\n", wdt_sta); + } /* Config watchdog reboot mode: * Clearing bits: 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6128df7eadaebcf7ff8d4c5492e3e0cfbab6e36 Gerrit-Change-Number: 62797 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/nissa/var/nivviks: Add TcssAuxori for nivviks
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62731 ) Change subject: mb/google/nissa/var/nivviks: Add TcssAuxori for nivviks ...................................................................... mb/google/nissa/var/nivviks: Add TcssAuxori for nivviks Enable SBU orientation handling by SoC for both USBC port0 and USBC port1. Nivviks USBC port0 do not have retimer, USBC port1 has redriver, but that do not flip the data lines. Hence we need to set bits for both the USBC ports. BRANCH:None TEST=emerge-nissa coreboot chromeos-bootimage. Flash the image on nivviks board and verified USBC display is working on both the ports in normal and inverted connections. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I219de6092ac9a9c773adbaa99f5a7d6196a2c937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62731 Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/nivviks/overridetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Reka Norman: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index c2eac2d..d423ffb 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -9,6 +9,15 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "TcssAuxOri" = "5" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" -- To view, visit https://review.coreboot.org/c/coreboot/+/62731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I219de6092ac9a9c773adbaa99f5a7d6196a2c937 Gerrit-Change-Number: 62731 Gerrit-PatchSet: 10 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: harsha.b.r(a)intel.com Gerrit-MessageType: merged

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coreboot-gerrit March 2022