coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/mediatek: Save dram info to cbmem
by Julius Werner (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Xixi Chen, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Save dram info to cbmem ...................................................................... Patch Set 25: (1 comment) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/61334/comment/fca5dca8_584b195e PS22, Line 123: p = (void *)((uintptr_t)mc + sizeof(*mc)); > Now I see what the problem is. […] I still can't reproduce locally if I make x a global tbh, although that would make sense since then the compiler can know for (pretty) sure that it's invalid. The difference here is that we're using a pointer, not just a local stack allocation, so then the compiler can't tell how it was allocated and if there's sufficient space reserved behind it. Anyway, as long as the problem is gone now that's good enough for me. -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 25 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 17:23:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add support for exclusive IDs
by Bhanu Prakash Maiya (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Robert Zieba, Raul Rangel, Karthik Ramasubramanian, Felix Held. Bhanu Prakash Maiya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62905 ) Change subject: util/spd_tools: Add support for exclusive IDs ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 Gerrit-Change-Number: 62905 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 18 Mar 2022 17:22:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add support for exclusive IDs
by Robert Zieba (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Raul Rangel, Bhanu Prakash Maiya, Karthik Ramasubramanian, Felix Held. Robert Zieba has removed Reka Norman from this change. ( https://review.coreboot.org/c/coreboot/+/62905 ) Change subject: util/spd_tools: Add support for exclusive IDs ...................................................................... Removed reviewer Reka Norman. -- To view, visit https://review.coreboot.org/c/coreboot/+/62905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 Gerrit-Change-Number: 62905 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: util/spd_tools: Add support for exclusive IDs
by Robert Zieba (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Reka Norman. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62905 ) Change subject: util/spd_tools: Add support for exclusive IDs ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/62905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 Gerrit-Change-Number: 62905 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Comment-Date: Fri, 18 Mar 2022 17:19:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Send EOP early in the boot sequence
by Tim Wawrzynczak (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Maulik V Vaghela. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62272 ) Change subject: soc/intel/adl: Send EOP early in the boot sequence ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/62272/comment/3477d9a8_513405f8 PS11, Line 158: Intel CSE team recommends to send EOP close to FW init (between FSP-S exit and : * current boot sequence) to reduce message response time from CSE hence moving : * sending EOP to earlier stage. > Sure, I got this - but why is that only relevant on alderlake? We didn't run into this issue on TGL b/c the FSP sent the EOP message IIRC (for chrome OS boards anyway) -- To view, visit https://review.coreboot.org/c/coreboot/+/62272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Gerrit-Change-Number: 62272 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 16:45:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MB
by Fred Reitberger (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Nikolai Vyssotski, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62926 ) Change subject: mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MB ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d Gerrit-Change-Number: 62926 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 18 Mar 2022 16:38:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MB
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Nikolai Vyssotski. Hello Nikolai Vyssotski, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62926 to review the following change. Change subject: mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MB ...................................................................... mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MB To have enough space in the A/B RW sections, increase those sizes to 4 MByte and decrease the RO section size to 6 MByte to free up the space needed for that. Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d --- M src/mainboard/amd/chausie/chromeos.fmd 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/62926/1 diff --git a/src/mainboard/amd/chausie/chromeos.fmd b/src/mainboard/amd/chausie/chromeos.fmd index e913e39..959a05c 100644 --- a/src/mainboard/amd/chausie/chromeos.fmd +++ b/src/mainboard/amd/chausie/chromeos.fmd @@ -2,12 +2,12 @@ SI_BIOS { EC 4K RW_MRC_CACHE(PRESERVE) 96K - RW_SECTION_A 3M { + RW_SECTION_A 4M { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 256 } - RW_SECTION_B 3M { + RW_SECTION_B 4M { VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 256 @@ -21,7 +21,7 @@ RW_NVRAM(PRESERVE) 20K SMMSTORE(PRESERVE) 4K RW_LEGACY(CBFS) - WP_RO@8M 8M { + WP_RO@10M 6M { RO_VPD(PRESERVE) 16K RO_SECTION { FMAP 2K -- To view, visit https://review.coreboot.org/c/coreboot/+/62926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d Gerrit-Change-Number: 62926 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/chausie: add APCB binaries if available
by Felix Held (Code Review) 18 Mar '22

18 Mar '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62925 ) Change subject: mb/amd/chausie: add APCB binaries if available ...................................................................... mb/amd/chausie: add APCB binaries if available The APCB files that provide the firmware components running on the PSP some mainboard-specific information like the DRAM interface configuration. Those files aren't yet in the upstream 3rdparty/blobs repository, so only add those files if they are present and print that no APCB was added and the image won't boot if they aren't present. TEST=Both cases behave as expected. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f --- M src/mainboard/amd/chausie/Makefile.inc 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/62925/1 diff --git a/src/mainboard/amd/chausie/Makefile.inc b/src/mainboard/amd/chausie/Makefile.inc index e494400..1e1b6d4 100644 --- a/src/mainboard/amd/chausie/Makefile.inc +++ b/src/mainboard/amd/chausie/Makefile.inc @@ -8,9 +8,12 @@ ramstage-y += chromeos.c ramstage-y += gpio.c -#TODO: add APCB binaries -#APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin -#APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4_DefaultRecovery.bin +ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin),) +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin +APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_FT6_DefaultRecovery.bin +else +$(info APCB sources not found. Skipping APCB. The resulting image won't boot.) +endif ifeq ($(CONFIG_CHAUSIE_HAVE_MCHP_FW),y) $(call add_intermediate, add_mchp_fw) -- To view, visit https://review.coreboot.org/c/coreboot/+/62925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f Gerrit-Change-Number: 62925 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/skyrim: Enable tis_plat_irq_status
by 9elements QA (Code Review) 18 Mar '22

18 Mar '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62873 ) Change subject: mb/google/skyrim: Enable tis_plat_irq_status ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 9 / 1 / 10 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/96180 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/96179 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/96178 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/96177 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/96176 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/96175 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/96174 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/96173 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/96172 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/96171 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/62873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5add694506ad089adcc8961f101bf507bc39a522 Gerrit-Change-Number: 62873 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 18 Mar 2022 16:32:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Add DXIO descriptors
by Jon Murphy (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Raul Rangel, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62903 to look at the new patch set (#9). Change subject: mb/google/skyrim: Add DXIO descriptors ...................................................................... mb/google/skyrim: Add DXIO descriptors Add Skyrim DXIO descriptors using info from AMD and skyrim bouard shematics. BUG=b:225179599 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 --- M src/mainboard/google/skyrim/port_descriptors.c M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h 3 files changed, 79 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/62903/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/62903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 Gerrit-Change-Number: 62903 Gerrit-PatchSet: 9 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022