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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62914
to look at the new patch set (#2).
Change subject: soc/intel/alderlake: Add UfsEnable parameter
......................................................................
soc/intel/alderlake: Add UfsEnable parameter
Add UFS enable based on devicetree on/off. And disable UFS port 2.
Per EDS#626817 PCH 600/700 only support 1 UFS port.
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Change-Id: Ic9b956204fb1001977d86c0d898b2734efb32271
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/62914/2
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Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62893 )
Change subject: mb/google/corsola: Revise power-on sequence of PS8640
......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62893/comment/f5b5d2cc_9092c580
PS5, Line 10: do
> does
Done
https://review.coreboot.org/c/coreboot/+/62893/comment/68404bcd_2e2c3a0f
PS5, Line 9: The power-on sequence of PS8640 needs to be modified because the
: waveform of power-on sequence do not meet the spec of PS8640.
> Is there a user noticeable display issue?
no, just not meet power-on spec measured by oscilloscope.
https://review.coreboot.org/c/coreboot/+/62893/comment/968402ab_76fbafac
PS5, Line 10: waveform of power-on sequence
> How do you measure it? […]
Done
https://review.coreboot.org/c/coreboot/+/62893/comment/b093a5e8_ee4dc024
PS5, Line 16: TEST=show fw display normally in krabby.
> Please document, that/if boot time is now 110 ms longer. […]
In normal boot flow, display will be disable, and we won't take that 110ms.
I also add the description in commit message.
https://review.coreboot.org/c/coreboot/+/62893/comment/d447db1c_85434b68
PS5, Line 17: result of waveform meets the spec.
> As the datasheet is not publicly accessible, what does it look like?
I add power-on sequence in commit message:
- set VDD12 to be 1.2V
- set VDD33 to be 3.3V
- pull hign PD#
- pull down RST#
- delay 2ms
- pull high RST#
- delay more than 50ms (55ms for margin)
- pull down RST#
- delay more than 50ms (55ms for margin)
- pull high RST#
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62893
to look at the new patch set (#6).
Change subject: mb/google/corsola: Revise power-on sequence of PS8640
......................................................................
mb/google/corsola: Revise power-on sequence of PS8640
The power-on sequence of PS8640 needs to be modified because the
waveform of power-on sequence which is measured with oscilloscope
does not meet the spec of PS8640.
The sequence is:
- set VDD12 to be 1.2V
- set VDD33 to be 3.3V
- pull hign PD#
- pull down RST#
- delay 2ms
- pull high RST#
- delay more than 50ms (55ms for margin)
- pull down RST#
- delay more than 50ms (55ms for margin)
- pull high RST#
This flow will increase 110ms if firmware display is enabled in
krabby. For normal booting flow, the firmware will not be enabled,
so it will meet boot time requirements of Chrome OS. (Less than 1s.)
Datasheet name: PS8640_DS_V1.4_20200210.docx.
Chapter: 14.
BUG=b:222650141
TEST=show fw display normally in krabby.
TEST=result of waveform meets the spec.
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3
---
M src/mainboard/google/corsola/display.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/62893/6
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Change subject: soc/intel/alderlake: Add UfsEnable parameter
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62914/comment/223ffe65_1127f5f8
PS1, Line 620: s_cfg->UfsEnable[0] = is_devfn_enabled(PCH_DEVFN_UFS);
This is very weird, as per EDS, ADL-N supports only 1 UFS controller but FSP code assumes/kept placeholder for 2 UFS controller and later relying on PMC register 0x1E44 to know if 2nd UFS controller is enable or not.
So, unfortunately we need to keep a comment somewhere saying UfsEnable[1] is false to avoid confusion in future.
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Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
......................................................................
Patch Set 44: Code-Review+2
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Change subject: util/cbmem: add an option to append timestamp
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62639/comment/5ec51b9a_66d686fe
PS2, Line 16: invoke new cbmem option
Please give an example.
File util/cbmem/cbmem.c:
https://review.coreboot.org/c/coreboot/+/62639/comment/c95bfea5_a3618670
PS2, Line 88: char *v = mapping->virt;
Excuse my ignorance, why is the const removed?
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Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
......................................................................
Patch Set 13:
(1 comment)
Patchset:
PS13:
> denverton_ns looks fine
Thanks Jeff
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Change subject: mb/google/corsola: Revise power-on sequence of PS8640
......................................................................
Patch Set 5:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62893/comment/6ba7a675_428d9ebb
PS5, Line 10: waveform of power-on sequence
How do you measure it?
> measured with oscilloscope
https://review.coreboot.org/c/coreboot/+/62893/comment/8395d12f_c54c833f
PS5, Line 9: The power-on sequence of PS8640 needs to be modified because the
: waveform of power-on sequence do not meet the spec of PS8640.
Is there a user noticeable display issue?
https://review.coreboot.org/c/coreboot/+/62893/comment/bb6bb56a_56263cbd
PS5, Line 10: do
does
https://review.coreboot.org/c/coreboot/+/62893/comment/9e3b9e29_f4d98fd1
PS5, Line 16: TEST=show fw display normally in krabby.
Please document, that/if boot time is now 110 ms longer. Are Chromium OS’ boottime requirements still met?
https://review.coreboot.org/c/coreboot/+/62893/comment/5ae29d1b_1adfd304
PS5, Line 17: result of waveform meets the spec.
As the datasheet is not publicly accessible, what does it look like?
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Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
......................................................................
Patch Set 44: Code-Review+1
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