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Change subject: mb/google/brya/vell: Move WWAN devices for vell
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62771/comment/4f064713_327659df
PS4, Line 9: This was to merge PCIe ACPI code to WWAN device.Also, RTD3 devices are add to overridetree.cb where WWAN is
: present for vell.
> please reflow for 72 characters wide
Done
File src/mainboard/google/brya/variants/vell/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62771/comment/d0ee6ac4_28896c7c
PS4, Line 168: # register "reset_delay_ms" = "1000"
> nit: remove this
Done
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Change subject: mb/google/brya/vell: Move WWAN devices for vell
......................................................................
mb/google/brya/vell: Move WWAN devices for vell
This was to merge PCIe ACPI code to WWAN device. Also, RTD3 devices are
add to overridetree.cb where WWAN is present for vell.
BUG=b:224214465
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b
---
M src/mainboard/google/brya/variants/vell/overridetree.cb
1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62771/6
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Change subject: mb/google/brya/vell: Move WWAN devices for vell
......................................................................
mb/google/brya/vell: Move WWAN devices for vell
This was to merge PCIe ACPI code to WWAN device. Also, RTD3 devices are
add to overridetree.cb where WWAN is present for vell.
BUG=b:224214465
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b
---
M src/mainboard/google/brya/variants/vell/overridetree.cb
1 file changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62771/5
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Change subject: Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially""
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
Patchset:
PS5:
I can reproduce the issue on my brya4es as well
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Change subject: soc/intel/common: Add IOE P2SB for TCSS
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/common/block/p2sb/ioe_p2sb.c:
https://review.coreboot.org/c/coreboot/+/62721/comment/b899a5da_0f4809f4
PS9, Line 26: p2sb_dev_enable_bar
Sorry, there was a typo. It should be PCI instead of PCH.
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Change subject: soc/intel/common: Add IOE P2SB for TCSS
......................................................................
soc/intel/common: Add IOE P2SB for TCSS
Meteor Lake has the IOE Die for TCSS. This change adds the IOE P2SB
sideband access and exposes API for TCSS usage.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19
Signed-off-by: John Zhao <john.zhao(a)intel.com>
---
M src/soc/intel/common/block/include/intelblocks/p2sb.h
M src/soc/intel/common/block/p2sb/Kconfig
M src/soc/intel/common/block/p2sb/Makefile.inc
A src/soc/intel/common/block/p2sb/ioe_p2sb.c
M src/soc/intel/common/block/p2sb/p2sb.c
5 files changed, 70 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/62721/9
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Change subject: mb/google/zork/var/gumboz: Add fw_config probe for ALC5682-VD & VS
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Hi Rob,
Could you please help to review?
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Change subject: qualcomm/sc7280: Add support for edp and mdp driver
......................................................................
Patch Set 13:
(2 comments)
File src/soc/qualcomm/sc7280/display/edp_ctrl.c:
https://review.coreboot.org/c/coreboot/+/61342/comment/a9b785fe_e951275b
PS13, Line 363: GPIO_PULL_DOWN, GPIO_2MA, GPIO_INPUT);
Unless you're explicitly trying to set a non-standard drive strength, you're supposed to just use gpio_input_pulldown() for this.
https://review.coreboot.org/c/coreboot/+/61342/comment/71897da9_d31b4861
PS13, Line 360: gpio_output(GPIO(80), 1);
: mdelay(20);
: gpio_configure(GPIO(60), GPIO_FUNC_GPIO,
: GPIO_PULL_DOWN, GPIO_2MA, GPIO_INPUT);
: mdelay(10);
: gpio_output(GPIO(8), 1);
: mdelay(20);
> any chance that we can clarify what these GPIOs are? Either #define them or at least add comments t […]
These almost certainly don't belong here anyway (maybe the HPD, if that's the only pin the SoC can possibly use for that functionality, but not the others). We already had display voltage rail control on Trogdor, why don't you just copy the way it was done there? Board-specific GPIO handling belongs in mainboard.c.
(FWIW some old Herobrine schematic I have lists GPIO8 as AP_SAR_SENSOR_SDA, not sure if that's still up to date, but you may want to double-check that number.)
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Change subject: mb/google/dedede/var/lantis: Add ELAN touchscreen support for Landrid
......................................................................
Patch Set 15:
(1 comment)
Patchset:
PS15:
> Hi Rob, […]
wrong CL
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Change subject: mb/google/dedede/var/lantis: Add ELAN touchscreen support for Landrid
......................................................................
Patch Set 15:
(1 comment)
Patchset:
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Hi Rob,
Could you please help to review?
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