coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: soc/mediatek: Save dram info to cbmem
by Julius Werner (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Xixi Chen, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Save dram info to cbmem ...................................................................... Patch Set 25: (1 comment) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/61334/comment/1f4500a9_bf1ba563 PS22, Line 123: p = (void *)((uintptr_t)mc + sizeof(*mc)); The problem with C99 variable-length arrays is that they make sizeof() illegal. I believe GCC happens to still allow it and return the right thing for them, but it's not officially supported, whereas sizeof() for the zero-length arrays is well-defined (by GCC). Anyway, this should work. It has always worked... I'm not sure what's suddenly going on here, this seems to have to do with the recent upgrade to GCC 11. (There have been some other strange bugs with that too, see CB:62828.) The warning description for -Warray-bounds explicitly says: > -Warray-bounds=1: This is the warning level of -Warray-bounds and is enabled by -Wall; higher levels are not, and must be explicitly requested. > > -Warray-bounds=2: This warning level also warns about out of bounds access for arrays at the end of a struct and for arrays accessed through pointers. This warning level may give a larger number of false positives and is deactivated by default. coreboot doesn't set -Warray-bounds=2 explicitly, so we should only be using -Warray-bounds=1, and this is an array at the end of a struct so it should be excluded by this check. Doesn't look like you've actually tried uploading this that way (or am I overlooking the Jenkins comment?), so are you sure that fails in the described way for the official compiler version? Only for one specific architecture or all of them? I've tried reproducing this to a minimal test case, but I can't really make it show up: struct mystruct { int a; struct { int b; } c[0]; }; int test(struct mystruct *x) { return x->c[2].b; } Not sure if I'm trying the wrong compiler version or there's something more complicated needed to trigger this? We should figure out exactly what causes it and then decide what to do (i.e. temporarily disable -Warray-bounds or something while we file a bug with GCC). Rewriting all clean variable-length structure accesses into raw pointer arithmetic doesn't seem the right way to deal with this to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 25 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 23:43:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` t...
by Nick Vaccaro (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Subrata Banik, Paul Menzel, Tim Wawrzynczak, Andrey Petrov. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62907 ) Change subject: Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially"" ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62907/comment/ba70ef19_39475817 PS3, Line 10: on an ADL brya4es. > Please document, where it hangs exactly. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d Gerrit-Change-Number: 62907 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 23:39:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` t...
by Nick Vaccaro (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Andrey Petrov. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62907 to look at the new patch set (#4). Change subject: Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially"" ...................................................................... Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially"" This reverts a change that was causing hangs and exceptions during boot on an ADL brya4es. The hang (or ACPI exception) occurs at what appears to be the end of detecting the cores, prior to the "Display FSP Version Info HOB" log being displayed : [DEBUG] Detected 10 core, 12 thread CPU. [DEBUG] Display FSP Version Info HOB This reverts commit 40ca79714ad7d5f2aa201d83db4d97f21260d924. BUG=b:224873032 TEST=`emerge-brya coreboot chromeos-bootimage`, flash and verify brya4es is able to successfully reboot 200 times without any issues. Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c 1 file changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/62907/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d Gerrit-Change-Number: 62907 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: Makefile: Add .SECONDARY
by Raul Rangel (Code Review) 18 Mar '22

18 Mar '22

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62398 ) Change subject: Makefile: Add .SECONDARY ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62398/comment/81c54021_116e813b PS2, Line 10: Setting .SECONDARY will prevent make from : deleting the files. > ... and also breaks/prevents partial rebuild :/ […] Can you try this out? ``` diff --git a/Makefile.inc b/Makefile.inc index ec2d097b2dda..279f8d480f03 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1115,6 +1115,10 @@ ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE) endif +# coreboot.pre doesn't follow the standard Make conventions. It gets modified +# by multiple rules, and thus we can't compute the dependencies correctly. +$(shell rm -f $(obj)/coreboot.pre) + ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/62398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657a696acc71d42ba94442d4754ee63efd3e6a74 Gerrit-Change-Number: 62398 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 17 Mar 2022 23:01:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Makefile: Add .SECONDARY
by Michael Niewöhner (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Raul Rangel. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62398 ) Change subject: Makefile: Add .SECONDARY ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62398/comment/0bb63365_7264812d PS2, Line 10: Setting .SECONDARY will prevent make from : deleting the files. ... and also breaks/prevents partial rebuild :/ test: ``` $ make ... $ make SeaBIOS Wait up to 500 ms for PS/2 keyboard controller initialization E: 'etc/ps2-keyboard-spinup' already in ROM image. E: Failed while operating on 'COREBOOT' region! E: The image will be left unmodified. make: *** [payloads/external/Makefile.inc:107: seabios_ps2_timeout] Error 1 ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/62398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657a696acc71d42ba94442d4754ee63efd3e6a74 Gerrit-Change-Number: 62398 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 17 Mar 2022 22:46:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Update coreboot.org PSP Firmware Integration Guide Documentation
by Altamshali Hirani (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Altamshali Hirani. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62910 to look at the new patch set (#2). Change subject: Update coreboot.org PSP Firmware Integration Guide Documentation ...................................................................... Update coreboot.org PSP Firmware Integration Guide Documentation Update coreboot.org PSP Firmware Documentation with current internal PSP documentation Signed-off-by: Altamshali Hirani <al.hirani(a)amd.corp-partner.google.com> Change-Id: I677f86614b0fdc6377fb2e27932ed3a8ded27102 --- M Documentation/soc/amd/psp_integration.md 1 file changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/62910/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I677f86614b0fdc6377fb2e27932ed3a8ded27102 Gerrit-Change-Number: 62910 Gerrit-PatchSet: 2 Gerrit-Owner: Altamshali Hirani <al.hirani13(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Altamshali Hirani <al.hirani13(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: Update Coreboot.org PSP Firmware Integration Guide Documentation
by Felix Singer (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Altamshali Hirani. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62910 ) Change subject: Update Coreboot.org PSP Firmware Integration Guide Documentation ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62910/comment/5edd4dbe_9b26f26e PS1, Line 7: Update Coreboot.org PSP Firmware Integration Guide Documentation docs/soc/amd: Update PSP Firmware Integration Guide https://review.coreboot.org/c/coreboot/+/62910/comment/8e875e33_5d033990 PS1, Line 9: Update Coreboot.org PSP Firmware Documentation with current internal PSP documentation Clearly state the changes that are being made and provide an explanation. File Documentation/soc/amd/psp_integration.md: https://review.coreboot.org/c/coreboot/+/62910/comment/15cfcedd_aadb697f PS1, Line 306: | | | | content is placed in Missing character at the end of the line -- To view, visit https://review.coreboot.org/c/coreboot/+/62910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I677f86614b0fdc6377fb2e27932ed3a8ded27102 Gerrit-Change-Number: 62910 Gerrit-PatchSet: 1 Gerrit-Owner: Altamshali Hirani <al.hirani13(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Altamshali Hirani <al.hirani13(a)gmail.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 22:27:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Allow for the tool to support additional PSP entries
by Altamshali Hirani (Code Review) 18 Mar '22

18 Mar '22

Altamshali Hirani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62911 ) Change subject: Allow for the tool to support additional PSP entries ...................................................................... Allow for the tool to support additional PSP entries Consolidate the MAX_BIOS_ENTRIES and MAX_PSP_ENTRIES definitions into one file Signed-off-by: Altamshali Hirani <al.hirani(a)amd.corp-partner.google.com> Change-Id: Ie3c64a1875010e7fb368967283df6baf1cc7ba8d --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/62911/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f5b73d2..ed8137b 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -343,9 +343,6 @@ { .type = AMD_BIOS_INVALID }, }; - -#define MAX_BIOS_ENTRIES 0x2f - typedef struct _context { char *rom; /* target buffer, size of flash device */ uint32_t rom_size; /* size of flash device */ diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 70afe3c..a6700a2 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -151,7 +151,7 @@ psp_directory_entry entries[]; } __attribute__((packed, aligned(16))) psp_directory_table; -#define MAX_PSP_ENTRIES 0x1f +#define MAX_PSP_ENTRIES 0x2f typedef struct _psp_combo_header { uint32_t cookie; @@ -210,6 +210,8 @@ bios_directory_entry entries[]; } bios_directory_table; +#define MAX_BIOS_ENTRIES 0x2f + #define BDT_LVL1 (1 << 0) #define BDT_LVL2 (1 << 1) #define BDT_LVL1_AB (1 << 2) -- To view, visit https://review.coreboot.org/c/coreboot/+/62911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3c64a1875010e7fb368967283df6baf1cc7ba8d Gerrit-Change-Number: 62911 Gerrit-PatchSet: 1 Gerrit-Owner: Altamshali Hirani <al.hirani13(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: Update Coreboot.org PSP Firmware Integration Guide Documentation
by Altamshali Hirani (Code Review) 18 Mar '22

18 Mar '22

Altamshali Hirani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62910 ) Change subject: Update Coreboot.org PSP Firmware Integration Guide Documentation ...................................................................... Update Coreboot.org PSP Firmware Integration Guide Documentation Update Coreboot.org PSP Firmware Documentation with current internal PSP documentation Signed-off-by: Altamshali Hirani <al.hirani(a)amd.corp-partner.google.com> Change-Id: I677f86614b0fdc6377fb2e27932ed3a8ded27102 --- M Documentation/soc/amd/psp_integration.md 1 file changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/62910/1 diff --git a/Documentation/soc/amd/psp_integration.md b/Documentation/soc/amd/psp_integration.md index 9c7b1be..3e9dd07 100755 --- a/Documentation/soc/amd/psp_integration.md +++ b/Documentation/soc/amd/psp_integration.md @@ -172,6 +172,10 @@ * Intermediate Key Encryption Key, used to decrypt encrypted firmware images. This is mandatory in order to support encrypted firmware. +**0x22**: PSP Token Unlock data +* Used to support time-bound Secure Debug unlock during boot. This entry may + be omitted if the Token Unlock debug feature is not required. + **0x24**: Security policy binary * A security policy is applied to restrict the untrusted access to security sensitive regions. @@ -200,10 +204,6 @@ **0x52**: PSP boot loader usermode OEM application * Supported only in certain SKUs. -**0x22**: PSP Token Unlock data -* Used to support time-bound Secure Debug unlock during boot. This entry may - be omitted if the Token Unlock debug feature is not required. - ### Firmware Version of Binaries Every firmware binary contains 256 bytes of a PSP Header, which includes @@ -302,15 +302,25 @@ +--------------+---------------+------------------+----------------------------+ | SubProgram | 0x03[2:0] | 3 | Specify the SubProgram | +--------------+---------------+------------------+----------------------------+ -| Reserved | 0x03[7:3] | 5 | Reserved - Set to zero | +| RomId | 0x03[4:3] | 2 | Which SPI device the | +| | | | content is placed in ++--------------+---------------+------------------+----------------------------+ +| Writeable | 0x03[5] | 1 | Region is writable or read | +| | | | only | ++--------------+---------------+------------------+----------------------------+ +| Reserved | 0x03[7:6] | 2 | Reserved - Set to zero | +--------------+---------------+------------------+----------------------------+ | Size | 0x04 | 32 | Memory Region Size | +--------------+---------------+------------------+----------------------------+ -| Source | 0x08 | 64 | Physical Address of SPIROM | +| Source | 0x08 | 62 | Physical Address of SPIROM | | Address | | | location where the data for| | | | | the corresponding entry is | | | | | located | +--------------+---------------+------------------+----------------------------+ +| Entry Address| 0x08 | 2 | Same as Entry Address Mode | +| Mode | | | in PSP directory table | +| | | | entry fields | ++--------------+---------------+------------------+----------------------------+ | Destination | 0x10 | 64 | Destination Address of | | Address | | | memory location where the | | | | | data for the corresponding | -- To view, visit https://review.coreboot.org/c/coreboot/+/62910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I677f86614b0fdc6377fb2e27932ed3a8ded27102 Gerrit-Change-Number: 62910 Gerrit-PatchSet: 1 Gerrit-Owner: Altamshali Hirani <al.hirani13(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: docs/contributing/gsoc: Add reference to easy projects
by Felix Singer (Code Review) 18 Mar '22

18 Mar '22

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62906 ) Change subject: docs/contributing/gsoc: Add reference to easy projects ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Landed the change early because it’s trivial and the GSoC guide should have the reference to the easy projects as early as possible. -- To view, visit https://review.coreboot.org/c/coreboot/+/62906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22e4a7c6385ffb9ba77e10edad41ef3d027ba694 Gerrit-Change-Number: 62906 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 17 Mar 2022 22:21:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022