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Change subject: mb/google/zork/var/dirinboz: Add fw_config probe for ALC5682-VD & VS
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
Hi Rob,
Could you please help to review?
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Change subject: Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially""
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62907/comment/9baa6dc9_d7799ab6
PS4, Line 12: ACPI
> `APIC`
Ack
https://review.coreboot.org/c/coreboot/+/62907/comment/cbafd907_3891d3d5
PS4, Line 12: end of detecting the cores,
> this is the FSP MP initialization sequence
Thanks.
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62907
to look at the new patch set (#5).
Change subject: Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially""
......................................................................
Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially""
This reverts a change that was causing hangs and exceptions during boot
on an ADL brya4es.
The hang (or APIC exception) occurs at what appears to be the FSP MP initialization
sequence, prior to the "Display FSP Version Info HOB" log being displayed :
[DEBUG] Detected 10 core, 12 thread CPU.
[DEBUG] Display FSP Version Info HOB
This reverts commit 40ca79714ad7d5f2aa201d83db4d97f21260d924.
BUG=b:224873032
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and verify brya4es
is able to successfully reboot 200 times without any issues.
Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
1 file changed, 17 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/62907/5
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61622 )
Change subject: mb/google/brya/{}: Add SBU orientation property for Type C Mux
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Patchset:
PS5:
Still didn't get it, since it worked w/wo this change
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Change subject: soc/intel/adl: Send EOP early in the boot sequence
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/alderlake/chip.c:
https://review.coreboot.org/c/coreboot/+/62272/comment/198f6a2b_6798a7f8
PS11, Line 158: Intel CSE team recommends to send EOP close to FW init (between FSP-S exit and
: * current boot sequence) to reduce message response time from CSE hence moving
: * sending EOP to earlier stage.
> what about cnl,tgl? is this a general recommendation?
The reason we are doing this is we have performance metrics to meet, and if you wait "too long", the CSE may start to become busy doing other things, and you end up polling for the response to EOP for dozens of milliseconds.
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Change subject: Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially""
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62907/comment/fb51f081_a4488c4b
PS4, Line 12: ACPI
`APIC`
https://review.coreboot.org/c/coreboot/+/62907/comment/899a5fd9_c2bfc555
PS4, Line 12: end of detecting the cores,
this is the FSP MP initialization sequence
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Change subject: [RFC]soc/intel/icelake: Drop unmaintained platform
......................................................................
Patch Set 3: Code-Review+2
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Change subject: [RFC]soc/intel/icelake: Drop unmaintained platform
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
rebased
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Change subject: [RFC]soc/intel/icelake: Drop unmaintained platform
......................................................................
[RFC]soc/intel/icelake: Drop unmaintained platform
The only user of this platform was the CRB board. From the looks of it
the code never was ready for production as only engineering sample
CPUID are supported.
Change-Id: I3ded90d2cc7595cddbf067a76cb9984936e1dcbf
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---
M Documentation/mainboard/index.md
D Documentation/mainboard/intel/icelake_rvp.md
D Documentation/soc/intel/icelake/iceLake_coreboot_development.md
D Documentation/soc/intel/icelake/index.md
M Documentation/soc/intel/index.md
D src/mainboard/intel/icelake_rvp/Kconfig
D src/mainboard/intel/icelake_rvp/Kconfig.name
D src/mainboard/intel/icelake_rvp/Makefile.inc
D src/mainboard/intel/icelake_rvp/board_id.c
D src/mainboard/intel/icelake_rvp/board_id.h
D src/mainboard/intel/icelake_rvp/board_info.txt
D src/mainboard/intel/icelake_rvp/bootblock.c
D src/mainboard/intel/icelake_rvp/chromeos.c
D src/mainboard/intel/icelake_rvp/chromeos.fmd
D src/mainboard/intel/icelake_rvp/dsdt.asl
D src/mainboard/intel/icelake_rvp/hda_verb.c
D src/mainboard/intel/icelake_rvp/mainboard.c
D src/mainboard/intel/icelake_rvp/romstage_fsp_params.c
D src/mainboard/intel/icelake_rvp/spd/Makefile.inc
D src/mainboard/intel/icelake_rvp/spd/empty.spd.hex
D src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex
D src/mainboard/intel/icelake_rvp/spd/spd.h
D src/mainboard/intel/icelake_rvp/spd/spd_util.c
D src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h
D src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h
D src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h
D src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h
D src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc
D src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
D src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c
D src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc
D src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
D src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c
M src/soc/intel/common/block/cpu/mp_init.c
D src/soc/intel/icelake/Kconfig
D src/soc/intel/icelake/Makefile.inc
D src/soc/intel/icelake/acpi.c
D src/soc/intel/icelake/acpi/gpio.asl
D src/soc/intel/icelake/acpi/pch_hda.asl
D src/soc/intel/icelake/acpi/pci_irqs.asl
D src/soc/intel/icelake/acpi/pcie.asl
D src/soc/intel/icelake/acpi/scs.asl
D src/soc/intel/icelake/acpi/serialio.asl
D src/soc/intel/icelake/acpi/southbridge.asl
D src/soc/intel/icelake/acpi/xhci.asl
D src/soc/intel/icelake/bootblock/bootblock.c
D src/soc/intel/icelake/bootblock/pch.c
D src/soc/intel/icelake/bootblock/report_platform.c
D src/soc/intel/icelake/chip.c
D src/soc/intel/icelake/chip.h
D src/soc/intel/icelake/cpu.c
D src/soc/intel/icelake/elog.c
D src/soc/intel/icelake/espi.c
D src/soc/intel/icelake/finalize.c
D src/soc/intel/icelake/fsp_params.c
D src/soc/intel/icelake/gpio.c
D src/soc/intel/icelake/gspi.c
D src/soc/intel/icelake/i2c.c
D src/soc/intel/icelake/include/soc/bootblock.h
D src/soc/intel/icelake/include/soc/cpu.h
D src/soc/intel/icelake/include/soc/espi.h
D src/soc/intel/icelake/include/soc/gpe.h
D src/soc/intel/icelake/include/soc/gpio.h
D src/soc/intel/icelake/include/soc/gpio_defs.h
D src/soc/intel/icelake/include/soc/gpio_soc_defs.h
D src/soc/intel/icelake/include/soc/iomap.h
D src/soc/intel/icelake/include/soc/irq.h
D src/soc/intel/icelake/include/soc/itss.h
D src/soc/intel/icelake/include/soc/me.h
D src/soc/intel/icelake/include/soc/msr.h
D src/soc/intel/icelake/include/soc/nvs.h
D src/soc/intel/icelake/include/soc/p2sb.h
D src/soc/intel/icelake/include/soc/pch.h
D src/soc/intel/icelake/include/soc/pci_devs.h
D src/soc/intel/icelake/include/soc/pcr_ids.h
D src/soc/intel/icelake/include/soc/pm.h
D src/soc/intel/icelake/include/soc/pmc.h
D src/soc/intel/icelake/include/soc/ramstage.h
D src/soc/intel/icelake/include/soc/romstage.h
D src/soc/intel/icelake/include/soc/serialio.h
D src/soc/intel/icelake/include/soc/smbus.h
D src/soc/intel/icelake/include/soc/soc_chip.h
D src/soc/intel/icelake/include/soc/systemagent.h
D src/soc/intel/icelake/include/soc/usb.h
D src/soc/intel/icelake/lockdown.c
D src/soc/intel/icelake/me.c
D src/soc/intel/icelake/p2sb.c
D src/soc/intel/icelake/pmc.c
D src/soc/intel/icelake/pmutil.c
D src/soc/intel/icelake/reset.c
D src/soc/intel/icelake/romstage/Makefile.inc
D src/soc/intel/icelake/romstage/fsp_params.c
D src/soc/intel/icelake/romstage/romstage.c
D src/soc/intel/icelake/romstage/systemagent.c
D src/soc/intel/icelake/sd.c
D src/soc/intel/icelake/smihandler.c
D src/soc/intel/icelake/spi.c
D src/soc/intel/icelake/systemagent.c
D src/soc/intel/icelake/uart.c
99 files changed, 0 insertions(+), 8,115 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/60053/3
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Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61342 )
Change subject: qualcomm/sc7280: Add support for edp and mdp driver
......................................................................
Patch Set 13:
(1 comment)
File src/soc/qualcomm/sc7280/display/edp_ctrl.c:
https://review.coreboot.org/c/coreboot/+/61342/comment/9a9dd9d4_09e3bdc2
PS13, Line 360: gpio_output(GPIO(80), 1);
: mdelay(20);
: gpio_configure(GPIO(60), GPIO_FUNC_GPIO,
: GPIO_PULL_DOWN, GPIO_2MA, GPIO_INPUT);
: mdelay(10);
: gpio_output(GPIO(8), 1);
: mdelay(20);
any chance that we can clarify what these GPIOs are? Either #define them or at least add comments to what these 3 GPIOs are.
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