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Change subject: mb/google/skyrim: Add DXIO descriptors
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/62903/comment/22dd2747_c84ba9d5
PS3, Line 10: #define WLAN_DEVFN PCIE_GPP_2_0_DEVFN
: #define SD_DEVFN PCIE_GPP_2_1_DEVFN
> looking at the schematics i wonder if the mapping between logical and physical lanes is a 1:1 mappin […]
maybe i looked at the wrong page of the schematics
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Andrey Petrov,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially""
......................................................................
Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially""
This reverts a change that was causing hangs and exceptions during boot
on an ADL brya4es.
This reverts commit 40ca79714ad7d5f2aa201d83db4d97f21260d924.
BUG=b:224873032
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and verify brya4es
is able to successfully reboot 200 times without any issues.
Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
1 file changed, 17 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/62907/3
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62907
to look at the new patch set (#2).
Change subject: Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially""
......................................................................
Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially""
This reverts a change that was causing hangs and exceptions during boot
on an ADL brya4es.
This reverts commit 40ca79714ad7d5f2aa201d83db4d97f21260d924.
BUG=b:224873032
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and verify brya4es
is able so successfully reboot 200 times without any issues.
Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
1 file changed, 17 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/62907/2
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Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
......................................................................
Patch Set 13: Code-Review+1
(1 comment)
Patchset:
PS13:
denverton_ns looks fine
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Change subject: mb/google/skyrim: Add DXIO descriptors
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/62903/comment/d148c451_0b5a3a3f
PS3, Line 10: #define WLAN_DEVFN PCIE_GPP_2_0_DEVFN
: #define SD_DEVFN PCIE_GPP_2_1_DEVFN
> i'm not certain if those device functions need to be swapped. […]
looking at the schematics i wonder if the mapping between logical and physical lanes is a 1:1 mapping or if it's jut the same numbers, but counted backwards. if it's counted backwards, this mapping would be correct, but i'm not sure if it's 1:1 or counted backwards
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Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62907 )
Change subject: Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially""
......................................................................
Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially""
This reverts a change that was causing hangs and exceptions during boot
on an ADL brya4es.
This reverts commit 40ca79714ad7d5f2aa201d83db4d97f21260d924.
BUG=b:224873032
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and verify brya4es
is able so successfully reboot 50 times without any issues.
Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
1 file changed, 17 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/62907/1
diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
index 50e35b0..9aef1b6 100644
--- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
+++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
@@ -94,10 +94,23 @@
/* Run on BSP */
procedure(argument);
- /* Run on APs */
- if (mp_run_on_aps((void *)procedure, argument,
- MP_RUN_ON_ALL_CPUS, timeout_usec) != CB_SUCCESS) {
- printk(BIOS_ERR, "%s: Exit with Failure\n", __func__);
+ /*
+ * Run on APs Serially
+ *
+ * FIXME: As per MP service specification, EDK2 is allowed to specify the mode
+ * in which a 'func' routine should be executed on APs (i.e. execute serially
+ * or concurrently).
+ *
+ * MP service API `StartupAllCPUs` doesn't specify such requirement.
+ * Hence, running the `CpuCacheInfoCollectCoreAndCacheData`
+ * (UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c#194)
+ * simultaneously on APs results in a coherency issue (hang while executing `func`)
+ * due to lack of acquiring a spin lock while accessing common data structure in
+ * multiprocessor environment.
+ */
+ if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, false) !=
+ CB_SUCCESS) {
+ printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__);
return FSP_NOT_STARTED;
}
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Change subject: soc/intel/denverton_ns/cpu: Get CPU frequencies for SMBIOS type 4
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
could you reword the commit message? ex: 'Tianocore reports correct CPU frequency rather than 0MHz'
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Change subject: ec/google/chromeec: add fan speed rpm control
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62789/comment/212ac72a_e1896a0c
PS2, Line 10:
Where is CFSP documented?
https://review.coreboot.org/c/coreboot/+/62789/comment/f6ff2d59_51032471
PS2, Line 13: TEST=Built and booted on ADL-P based Brya system
And then? How to verified the fan speed?
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Change subject: Documentation/contributing/projects: Add "easy projects" section
......................................................................
Patch Set 9: Code-Review+1
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