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Change subject: util/cbmem: Keep original Total Time calculation when no negative timestamps
......................................................................
Patch Set 6: Code-Review+1
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Change subject: mb/google/brya/var/primus{4es}: add delay time to rtd3-cold
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62949/comment/41c9f1b3_9329b2d3
PS3, Line 12:
> Hi, […]
I am unable to access it. Plesae add the document name, revision and chapter to the commit message.
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Change subject: drivers/tpm/cr50: Use cr50_get_firmware_version in get_board_cfg
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Patch Set 3: Code-Review+1
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Change subject: mb/google/brya/var/primus{4es}: add delay time to rtd3-cold
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62949/comment/020e3a1f_e192a43d
PS3, Line 14:
`TEST=...`
how did you test?
`BRANCH=firmware-brya-14505.B`
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Change subject: mb/google/brya/var/primus{4es}: add delay time to rtd3-cold
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Patchset:
PS3:
Have you verified that adding 72ms to resume does not cause the power_Resume test to fail?
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Hello build bot (Jenkins), Subrata Banik, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62964
to look at the new patch set (#3).
Change subject: drivers/tpm/cr50: Use cr50_get_firmware_version in get_board_cfg
......................................................................
drivers/tpm/cr50: Use cr50_get_firmware_version in get_board_cfg
cr50_get_board_cfg() may be called in ramstage for some mainboards in
order to determine the BOARD_CFG register's value. The code was
written assuming that the firmware version was already retrieved, but
for boards calling this in ramstage, this is not the case. Therefore,
instead of using the cached cr50_firmware_version (which is all 0s in
ramstage at that time), use the cr50_get_firmware_version function
instead.
BUG=b:225206079, b:220685274
BRANCH=firmware-brya-14505.B
TEST=boot on brya0 and see:
[INFO ] Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.93/cr50_v3.94
[INFO ] Enabling GPIO PM b/c CR50 has long IRQ pulse support
in the logs.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Ia6e5f4965a8852793d2f95e6eb21ea87860335a9
---
M src/drivers/tpm/cr50.c
1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/62964/3
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62709 )
Change subject: commonlib/timestamp_serialized: Add timestamp enum to name mapping
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
File src/commonlib/include/commonlib/timestamp_serialized.h:
https://review.coreboot.org/c/coreboot/+/62709/comment/3cdecf2b_e752e45e
PS7, Line 169: ts_name_def
nit: not really a function-like macro, so the name should be in ALL_CAPS
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Hello Subrata Banik, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62964
to look at the new patch set (#2).
Change subject: drivers/tpm/cr50: Use cr50_get_firmware_version in get_board_cfg
......................................................................
drivers/tpm/cr50: Use cr50_get_firmware_version in get_board_cfg
cr50_get_board_cfg() may be called in ramstage for some mainboards in
order to determine the BOARD_CFG register's value. The code was
written assuming that the firmware version was already retrieved, but
for boards calling this in ramstage, this is not the case. Therefore,
instead of using the cached cr50_firmware_version (which is all 0s in
ramstage at that time), use the cr50_get_firmware_version function
instead.
BUG=b:225206079, b:220685274
TEST=boot on brya0 and see:
[INFO ] Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.93/cr50_v3.94
[INFO ] Enabling GPIO PM b/c CR50 has long IRQ pulse support
in the logs.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Ia6e5f4965a8852793d2f95e6eb21ea87860335a9
---
M src/drivers/tpm/cr50.c
1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/62964/2
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Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62964 )
Change subject: drivers/tpm/cr50: Use cr50_get_firmware_version in get_board_cfg
......................................................................
drivers/tpm/cr50: Use cr50_get_firmware_version in get_board_cfg
cr50_get_board_cfg() may be called in ramstage for some mainboards in order
to determine the BOARD_CFG register's value. The code was written assuming that
the firmware version was already retrieved, but for boards calling this in
ramstage, this is not the case. Therefore, instead of using the cached
cr50_firmware_version (which is all 0s in ramstage at that time), use
the cr50_get_firmware_version function instead.
BUG=b:225206079, b:220685274
TEST=boot on brya0 and see:
[INFO ] Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.93/cr50_v3.94
[INFO ] Enabling GPIO PM b/c CR50 has long IRQ pulse support
in the logs.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Ia6e5f4965a8852793d2f95e6eb21ea87860335a9
---
M src/drivers/tpm/cr50.c
1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/62964/1
diff --git a/src/drivers/tpm/cr50.c b/src/drivers/tpm/cr50.c
index f96e174..69d53a9 100644
--- a/src/drivers/tpm/cr50.c
+++ b/src/drivers/tpm/cr50.c
@@ -74,9 +74,13 @@
*/
static uint32_t cr50_get_board_cfg(void)
{
+ struct cr50_firmware_version ver;
uint32_t value;
- if (!cr50_fw_supports_board_cfg(&cr50_firmware_version))
+ if (cr50_get_firmware_version(&ver) != CB_SUCCESS)
+ return 0;
+
+ if (!cr50_fw_supports_board_cfg(&ver))
return 0;
const enum cb_err ret = tis_vendor_read(get_reg_addr(CR50_BOARD_CFG_REG), &value,
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