coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: util/cbmem: Keep original Total Time calculation when no negative tim...
by Bora Guvendik (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Selma Bensaid, Paul Menzel, Tim Wawrzynczak. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61839 ) Change subject: util/cbmem: Keep original Total Time calculation when no negative timestamps ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61839/comment/5789f752_5fef83e4 PS5, Line 9: "Total time" calculation changed after CL 59555 to include : "1st timestamp" value in the calculation. This patch restores : original Total Time calculation where "1st timetamp" is : subtracted from "jumping to kernel". If pre CPU reset timestamps : are added (negative timestamps), "Total time" calculation still : includes the pre-reset time as expected. > Reflow for 72 characters per line? Done https://review.coreboot.org/c/coreboot/+/61839/comment/a98d72ea_c5d46cef PS5, Line 35: TEST=Boot to OS, check cbmem -t > Please add the board you go the timestamps from. Done File util/cbmem/cbmem.c: https://review.coreboot.org/c/coreboot/+/61839/comment/4bd5915d_e09c828d PS5, Line 648: prev_stamp = tst_p->base_time; > If one branch requires brackets, all branches do. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0442f796b03731df3b869aea32d40ed94cabdce0 Gerrit-Change-Number: 61839 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 17:38:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/psp_verstage: Write postcodes after ESPI init
by Karthik Ramasubramanian (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Jon Murphy, Rob Barnes, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Jon Murphy, Rob Barnes, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62880 to look at the new patch set (#2). Change subject: soc/amd/common/psp_verstage: Write postcodes after ESPI init ...................................................................... soc/amd/common/psp_verstage: Write postcodes after ESPI init On boards where PSP uses ESPI to write postcodes, update the verstage to do it after ESPI initialization. BUG=b:224543620 TEST=Build and boot to OS in Nipperkin. Ensure that there are no attempts to write the post code from PSP verstage before ESPI initialization. Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/psp_verstage/psp_verstage.c 2 files changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/62880/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364 Gerrit-Change-Number: 62880 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Avinash Alevoor Gerrit-CC: Mohan Viswanathan Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
by Ravishankar Sarawadi (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Felix Singer, Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Paul Menzel, Raj Astekar. Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62772 ) Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock ...................................................................... Patch Set 5: (1 comment) Patchset: PS4: > > @subrata, are you suggesting SoC and MB bootblock ONLY code should compile and boot till last post […] Any guidance/documentation on HOW-TOs for stage-wise Make build setup? Wondering when building coreboot.rom if it stubs out stages if not included. -- To view, visit https://review.coreboot.org/c/coreboot/+/62772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 Gerrit-Change-Number: 62772 Gerrit-PatchSet: 5 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 17:37:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support
by Michael Niewöhner (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support ...................................................................... Patch Set 3: (1 comment) File src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62498/comment/40d28377_cf2d834b PS1, Line 58: register "LpmStateDisableMask" = " : LPM_S0i2_1 | : LPM_S0i2_2 | : LPM_S0i3_1 | : LPM_S0i3_2 | : LPM_S0i3_3 | : LPM_S0i3_4 : > Yes, but it does not handle the LPM_S0i2_1. […] Why does s0i2.1 it have to be disabled on that board? -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 17:34:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbmem: Keep original Total Time calculation when no negative tim...
by Bora Guvendik (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Bora Guvendik, Subrata Banik, Maulik V Vaghela, Selma Bensaid, Tim Wawrzynczak. Hello build bot (Jenkins), Subrata Banik, Maulik V Vaghela, Selma Bensaid, Paul Menzel, Tim Wawrzynczak, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61839 to look at the new patch set (#6). Change subject: util/cbmem: Keep original Total Time calculation when no negative timestamps ...................................................................... util/cbmem: Keep original Total Time calculation when no negative timestamps "Total time" calculation changed after CL 59555 to include "1st timestamp" value in the calculation. This patch restores original Total Time calculation where "1st timetamp" is subtracted from "jumping to kernel". If pre CPU reset timestamps are added (negative timestamps), "Total time" calculation still includes the pre-reset time as expected. 1) Before https://review.coreboot.org/c/coreboot/+/59555: 0:1st timestamp 225,897 1101:jumping to kernel 1,238,218 (16,316) Total Time: 1,012,281 2) After https://review.coreboot.org/c/coreboot/+/59555: 0:1st timestamp 225,897 1101:jumping to kernel 1,238,218 (16,316) Total Time: 1,238,178 3) After this patch: 0:1st timestamp 225,897 (0) 1101:jumping to kernel 1,238,218 (16,316) Total Time: 1,012,281 BUG=none TEST=Boot to OS, check cbmem -t on Redrix board Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I0442f796b03731df3b869aea32d40ed94cabdce0 --- M util/cbmem/cbmem.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/61839/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0442f796b03731df3b869aea32d40ed94cabdce0 Gerrit-Change-Number: 61839 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/{}: Add SBU orientation property for Type C Mux
by Prashant Malani (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Meera Ravindranath, Nick Vaccaro, Prashant Malani. Prashant Malani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61622 ) Change subject: mb/google/brya/{}: Add SBU orientation property for Type C Mux ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Friendly ping, Meera...could have mark this as verified once Intel has tested it on other variants? This is an FSI blocker, so we need this in urgently. -- To view, visit https://review.coreboot.org/c/coreboot/+/61622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f7f9554b75f4d62298aac9938e66c71c3e7cee9 Gerrit-Change-Number: 61622 Gerrit-PatchSet: 5 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Prashant Malani <pmalani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 17:28:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in blobs[master]: mb/google/guybrush: Update APCB file
by Karthik Ramasubramanian (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Robert Zieba, Raul Rangel, Martin L Roth, Patrick Georgi, Rob Barnes, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/62963 ) Change subject: mb/google/guybrush: Update APCB file ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: Martin/Patrick, What is the process for CLs in blobs git submodule? Does buildbot set the Verified + 1? Can anyone with coreboot submit permissions submit the CLs in blobs submodule? Is it recommended to wait for obligatory 24 hours to submit the changes here? -- To view, visit https://review.coreboot.org/c/blobs/+/62963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: Ifbfe2c61c42cd503a70fd84c51ce184c40fed318 Gerrit-Change-Number: 62963 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 21 Mar 2022 17:24:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/chausie: add APCB binaries if available
by Felix Held (Code Review) 21 Mar '22

21 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62925 ) Change subject: mb/amd/chausie: add APCB binaries if available ...................................................................... mb/amd/chausie: add APCB binaries if available The APCB files that provide the firmware components running on the PSP some mainboard-specific information like the DRAM interface configuration. Those files aren't yet in the upstream 3rdparty/blobs repository, so only add those files if they are present and print that no APCB was added and the image won't boot if they aren't present. TEST=Both cases behave as expected. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62925 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/mainboard/amd/chausie/Makefile.inc 1 file changed, 6 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/mainboard/amd/chausie/Makefile.inc b/src/mainboard/amd/chausie/Makefile.inc index e494400..1e1b6d4 100644 --- a/src/mainboard/amd/chausie/Makefile.inc +++ b/src/mainboard/amd/chausie/Makefile.inc @@ -8,9 +8,12 @@ ramstage-y += chromeos.c ramstage-y += gpio.c -#TODO: add APCB binaries -#APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin -#APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4_DefaultRecovery.bin +ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin),) +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin +APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_FT6_DefaultRecovery.bin +else +$(info APCB sources not found. Skipping APCB. The resulting image won't boot.) +endif ifeq ($(CONFIG_CHAUSIE_HAVE_MCHP_FW),y) $(call add_intermediate, add_mchp_fw) -- To view, visit https://review.coreboot.org/c/coreboot/+/62925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f Gerrit-Change-Number: 62925 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/chausie: add APCB binaries if available
by Fred Reitberger (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Jason Glenesk, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62925 ) Change subject: mb/amd/chausie: add APCB binaries if available ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f Gerrit-Change-Number: 62925 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 21 Mar 2022 17:22:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MB
by Felix Held (Code Review) 21 Mar '22

21 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62926 ) Change subject: mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MB ...................................................................... mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MB To have enough space in the A/B RW sections, increase those sizes to 4 MByte and decrease the RO section size to 6 MByte to free up the space needed for that. Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62926 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/mainboard/amd/chausie/chromeos.fmd 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/mainboard/amd/chausie/chromeos.fmd b/src/mainboard/amd/chausie/chromeos.fmd index e913e39..959a05c 100644 --- a/src/mainboard/amd/chausie/chromeos.fmd +++ b/src/mainboard/amd/chausie/chromeos.fmd @@ -2,12 +2,12 @@ SI_BIOS { EC 4K RW_MRC_CACHE(PRESERVE) 96K - RW_SECTION_A 3M { + RW_SECTION_A 4M { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 256 } - RW_SECTION_B 3M { + RW_SECTION_B 4M { VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 256 @@ -21,7 +21,7 @@ RW_NVRAM(PRESERVE) 20K SMMSTORE(PRESERVE) 4K RW_LEGACY(CBFS) - WP_RO@8M 8M { + WP_RO@10M 6M { RO_VPD(PRESERVE) 16K RO_SECTION { FMAP 2K -- To view, visit https://review.coreboot.org/c/coreboot/+/62926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d Gerrit-Change-Number: 62926 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2022