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Change subject: [RFC]device/device.h: Remove struct bus linked list
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
It looks like there is a lot of sibling bus ops in coreboot...
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Change subject: soc/intel/common: Configure TCSS access through IOE P2SB
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS9:
> possible to split this cl into 2 parts […]
It would be fine to split into soc and platforms for new functions. I recall it would be preferable to put them together in order to avoid breaking existent functions.
Subrata, I am off this week. So please feel free to update.
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Change subject: util/cbmem: Add FlameGraph-compatible timestamps output
......................................................................
Patch Set 11:
(6 comments)
File src/commonlib/include/commonlib/timestamp_serialized.h:
https://review.coreboot.org/c/coreboot/+/62474/comment/2b1adfe7_0d5c82a3
PS7, Line 454: uint32_t id_end;
> It won't work. Look at TS_COPYVPD_START. It has two possible ends. […]
Hmm... okay, that's an odd case. Is that the only one? Even though the code is written like that I don't think there's actually any board that has an RW VPD but no RO VPD in practice.
I think having them all in one macro has the benefit that when people add new timestamps, they are more explicitly prompted to add a possible end symbol by the structure of the table. If you have the ranges hidden somewhere else in another table, I think it's a lot more likely people will forget to add new entries down there.
If you lay out the struct as uint32_t, uint32_t, char *, char *, then the second uint32_t will be hidden by padding anyway on 64-bit systems and doesn't make the table larger. Also, I wouldn't worry about the size too much... coreboot shouldn't really be including that list anyway. (CONFIG_TIMESTAMPS_ON_CONSOLE is a really terrible design one way or another tbh. If anyone actually wants to use that and have it be efficient, they should redesign it to a point where it only includes strings for timestamps that each stage actually uses, rather than every possible special vendor timestamp there is.)
File util/cbmem/cbmem.c:
https://review.coreboot.org/c/coreboot/+/62474/comment/74dd0894_fd4f680f
PS8, Line 629: ::
> yeah I kinda like the `::`, I can't think of anything better
Oh, I thought this was given by the flame graph tool? Or is this how it will look like in the flame graph (i.e. it will show `TS_VBOOT_START::TS_VBOOT_END` as the label of one section)? Could maybe also use `->` or `<->`? (I assume spaces are illegal? Otherwise some spaces would probably help readability.)
File util/cbmem/cbmem.c:
https://review.coreboot.org/c/coreboot/+/62474/comment/4c6cdd3c_96b78b23
PS11, Line 630: if (i < stacklvl)
nit: I think if you add ` || last_part` here...
https://review.coreboot.org/c/coreboot/+/62474/comment/758c6476_5dfdb168
PS11, Line 634: if (stacklvl > 0)
...you can take this out.
https://review.coreboot.org/c/coreboot/+/62474/comment/d4185804_c4f9479e
PS11, Line 727: sorted_tst_p->entries[match].entry_stamp;
nit: I think adding base_time here would make it easier to understand than subtracting it below (because then stamp and match_stamp are constructed in a more symmetrical way).
https://review.coreboot.org/c/coreboot/+/62474/comment/961388ff_d7f54bf3
PS11, Line 1384: enum timestamps_print_type timestamp_type = TIMESTAMPS_PRINT_NORMAL;
If you have an enum anyway maybe also roll print_timestamps into that (i.e. default to TIMESTAMPS_PRINT_NONE)?
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Change subject: drivers/tpm/cr50: Use cr50_get_firmware_version in get_board_cfg
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/common/block/psp: Add platform secure boot support
......................................................................
Patch Set 14:
(1 comment)
File src/soc/amd/common/block/psp/Kconfig:
https://review.coreboot.org/c/coreboot/+/60968/comment/07b2e085_7e707a85
PS12, Line 55: coreboot ROM is properly signed and can not be disabled once fused.
> Updated document reference for PSB Feature. […]
Ack
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Change subject: [RFC]device/device.h: Remove struct bus linked list
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Let's see if this blows up somewhere...
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Al Hirani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62966 )
Change subject: Reorder PSP Directory Table Types | Update PSP Firmware Integration Guide Documentation
......................................................................
Reorder PSP Directory Table Types | Update PSP Firmware Integration Guide Documentation
Update PSP Firmware Documentation with current internal PSP documentation
Reorder PSP Directory Table Types - move 0x22 after 0x21
Signed-off-by: Altamshali Hirani <al.hirani(a)amd.corp-partner.google.com>
Change-Id: I5fb893a769fe0d870e14e68183fc7e49421605bd
---
M Documentation/soc/amd/psp_integration.md
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/62966/1
diff --git a/Documentation/soc/amd/psp_integration.md b/Documentation/soc/amd/psp_integration.md
index dd57e46..c85948c 100755
--- a/Documentation/soc/amd/psp_integration.md
+++ b/Documentation/soc/amd/psp_integration.md
@@ -172,6 +172,10 @@
* Intermediate Key Encryption Key, used to decrypt encrypted firmware images.
This is mandatory in order to support encrypted firmware.
+**0x22**: PSP Token Unlock data
+* Used to support time-bound Secure Debug unlock during boot. This entry may
+ be omitted if the Token Unlock debug feature is not required.
+
**0x24**: Security policy binary
* A security policy is applied to restrict the untrusted access to security
sensitive regions.
@@ -200,10 +204,6 @@
**0x52**: PSP boot loader usermode OEM application
* Supported only in certain SKUs.
-**0x22**: PSP Token Unlock data
-* Used to support time-bound Secure Debug unlock during boot. This entry may
- be omitted if the Token Unlock debug feature is not required.
-
### Firmware Version of Binaries
Every firmware binary contains 256 bytes of a PSP Header, which includes
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Hello Arthur Heymans,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/62965
to review the following change.
Change subject: [RFC]device/device.h: Remove struct bus linked list
......................................................................
[RFC]device/device.h: Remove struct bus linked list
The current allocator code never loops over the next busses so remove
this linked list and always assume one downstream bus per device.
Change-Id: Ib757957d6470111651f88b550df06c4c953b777f
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/include/device/device.h
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/62965/1
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 237d836..938ab5e 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -77,7 +77,6 @@
DEVTREE_CONST struct device *dev; /* This bridge device */
DEVTREE_CONST struct device *children; /* devices behind this bridge */
- DEVTREE_CONST struct bus *next; /* The next bridge on this device */
unsigned int bridge_ctrl; /* Bridge control register */
uint16_t bridge_cmd; /* Bridge command register */
unsigned char link_num; /* The index of this link */
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