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Change subject: commonlib/bsd/helpers: Move STRINGIFY() from string.h
......................................................................
Patch Set 2:
(1 comment)
File src/commonlib/bsd/include/commonlib/bsd/helpers.h:
https://review.coreboot.org/c/coreboot/+/62921/comment/7fca6c6a_2727c19e
PS2, Line 15: #define ALIGN(x, a) __ALIGN_MASK(x, (__typeof__(x))(a)-1UL)
> ALIGN(), ALIGN_UP(), GiB, etc. […]
Right... now that we integrated commonlib/bsd into libpayload, we should be deduplicating those macros. Can you #include <commonlib/bsd/helpers.h> from <libpayload.h> and remove the duplicate libpayload versions (in another patch before this one)?
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Change subject: util/cbmem: Keep original Total Time calculation when no negative timestamps
......................................................................
Patch Set 6: Code-Review+2
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Change subject: util/spd_tools: Add support for exclusive IDs
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> i'm not sure if this is the correct approach or if this and the next one just adds a workaround arou […]
This change is not impacting the default behavior of the SPD generation tool or SPD ID generation tool. This change just updates the tool to use the hint from the mainboard/variant to reserve certain SPD IDs exclusively. There has been precedence in the past.
This support is required because of the ABL requirement to train memory with specific tuning values for certain memory parts eventhough their characteristics is identical to other parts. It is not identifying single vs dual rank memory parts. Rather it is about training certain(not all) Samsung parts with specific tuning values.
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Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
......................................................................
Patch Set 44:
(1 comment)
File src/drivers/intel/fsp2_0/include/fsp/util.h:
https://review.coreboot.org/c/coreboot/+/59638/comment/dcf83615_c59a5105
PS44, Line 32: efi_physical_address
> Hi Felix. We used the efi_physical_address here to keep it similar to the structure definition in FSP 2.3 arch spec doc
I agree with Anil and efi_physical_address is typedef to uint64_t inside efi_datatype.h
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Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
......................................................................
Patch Set 44:
(1 comment)
File src/drivers/intel/fsp2_0/include/fsp/util.h:
https://review.coreboot.org/c/coreboot/+/59638/comment/0ea1a2aa_0aeff176
PS44, Line 32: efi_physical_address
> using uint64_t instead would make the data type size more obvious
Hi Felix. We used the efi_physical_address here to keep it similar to the structure definition in FSP 2.3 arch spec doc
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Change subject: mb/google/brya/{}: Add SBU orientation property for Type C Mux
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61622/comment/6eff300d_461190ba
PS5, Line 7: /{}
What do the brackets denote?
https://review.coreboot.org/c/coreboot/+/61622/comment/132e6f2b_5d5596a6
PS5, Line 8:
Please describe the current problem.
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Change subject: util/spd_tools: Add support for exclusive IDs
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
i'm not sure if this is the correct approach or if this and the next one just adds a workaround around another bug. the difference of the memory parts seems to be single vs dual rank and i'd assume that this should result in different SPD images which then won't require this workaround
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Change subject: mb/google/guybrush: Enable PSP_POSTCODES_ON_ESPI config
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I am abandonding this CL since PSP uses ESPI by default to write postcodes. Hence it is enabled at the SoC Kconfig.
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Change subject: soc/amd/common/psp_verstage: Write postcodes after ESPI init
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/cezanne/Kconfig:
https://review.coreboot.org/c/coreboot/+/62880/comment/37c0ed92_6de53aaf
PS1, Line 348: PSP_POSTCODES_ON_ESPI
> Yes, PSP uses ESPI to write postcodes(Prerequisite is the ESPI should be initialized). […]
Ack. Then I updated the config to be default y.
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