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Change subject: mb/google/brya/var/taeko: Enable Genesys L1 entry delay
......................................................................
Patch Set 4: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62918/comment/0b9245d8_e845072a
PS4, Line 7: L1 entry
`L1 max entry delay`
https://review.coreboot.org/c/coreboot/+/62918/comment/1e77274d_bdadbe56
PS4, Line 10: eMMC can not detect issue.
Add something like:
```
The workaround causes the eMMC controller to not enter its L1
during the boot process
```
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Change subject: mb/amd/chausie: add APCB binaries if available
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Patch Set 2: Code-Review+2
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Change subject: mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MB
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Patch Set 2: Code-Review+2
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Change subject: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
......................................................................
Patch Set 9:
(2 comments)
Patchset:
PS9:
Please split the mainboard and SoC changes into 2 separate commits
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62919/comment/be1929f5_6cfa52f7
PS9, Line 300: int
nit: `unsigned int`
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Change subject: util/spd_tools: Add support for exclusive IDs
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Patch Set 8: Code-Review+2
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Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
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Patch Set 9:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62919/comment/a7ead463_d3ef6950
PS7, Line 643: s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->PcieRpAspm);
> ok. understood.
Done
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Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
Patch Set 35:
(3 comments)
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/61259/comment/9cc6f190_d10f32ae
PS34, Line 183: assert(gpp_req_index >= 0 && gpp_req_index < gpp_clk_config_num);
> by default asserts aren't fatal, so it'll complain but still continue; not sure if this is intended […]
Done
https://review.coreboot.org/c/coreboot/+/61259/comment/a6d3a55e_d2d75ea2
PS34, Line 196: /* PCIe devices haven't been fully set up yet, so directly read the vendor id
> the code below reads both the vendor and product id; both ids are just 16 bit with the vendor id sta […]
Done
https://review.coreboot.org/c/coreboot/+/61259/comment/7c421189_af00ac33
PS34, Line 200: && (id != 0x0000ffff) && (id != 0xffff0000)
> not sure if those two cases are needed. […]
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Change subject: mb/google/guybrush: Update APCB file
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/blobs/+/62963/comment/c739c8c2_c68761a3
PS2, Line 9: is
> Nit: not required.
Done
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Hello Raul Rangel, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/blobs/+/62963
to look at the new patch set (#3).
Change subject: mb/google/guybrush: Update APCB file
......................................................................
mb/google/guybrush: Update APCB file
The existing APCB file only has 4 SPD slots. This will not be enough
for DeWatt devices due to upcoming changes in how RAM IDs are allocated
for that variant. This commit updates the APCB file to have enough
slots.
BUG=b:224884904
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: Ifbfe2c61c42cd503a70fd84c51ce184c40fed318
---
M mainboard/google/guybrush/APCB_CZN_D4.bin
1 file changed, 0 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/blobs refs/changes/63/62963/3
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