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Change subject: intelblocks/pep: Add display on/off notifications and handle TBT displays
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62494/comment/8473c9f6_8838bc7d
PS3, Line 7: intelblocks/pep: Add display on/off notifications and handle TBT displays
nit: 72 characters wide for commit msgs
https://review.coreboot.org/c/coreboot/+/62494/comment/df119261_1420aa3a
PS3, Line 8:
: Add display on and off notifications which call mainboard hooks if
: present. This allows to handle some board specific functions in user
: absence or presence (whe ndisplay goes off from inactivity or on from
: activity).
:
: Additionally notify IOM to enable or disable TBT displays on S0ix
: exit and entry respectively.
These are kind of unrelated changes, mind splitting this into two patches?
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Change subject: [set offset, enable rth and energy report]
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62959/comment/bdf86733_92a2c47d
PS1, Line 7: [set offset, enable rth and energy report]
Please look through `git log` how to write a commit message and amend it.
Patchset:
PS1:
Thank you for the patch and welcome to coreboot.
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Change subject: soc/intel/alderlake: Add UfsEnable parameter
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Patch Set 2: Code-Review-1
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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> From the FSP code, Index one shouldn't work, right? […]
PchGetMaxUfsNum should be 1 if ADL only support 1 UFS pre EDS.
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Change subject: soc/intel/alderlake: Add support for UFS controller
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Patch Set 1:
(1 comment)
Patchset:
PS1:
But 1 shouldn't worked with the FSP code.. Could you add log in the FSP to see what is the pch_max?
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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62856/comment/86cc4bf4_1f3377a4
PS1, Line 619: s_cfg->UfsEnable[1] = 0;
> Thanks Subrata, Yeah it's weird that we're enabling index 1 instead of 0. […]
We will come back on this with supporting documents, but enabling index 0 fails to boot via UFS. Needs index 1(controller 1) to be enabled for UFS boot.
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Change subject: soc/intel/common/block: Add Intel common UFS code support
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> It looks like we don't have any specialized method in dev_ops, why can't we just use generic pci dri […]
Point, tried using the generic driver and it works. Will abandon this CL.
Thanks for the suggestion.
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Change subject: mb/google/brask/variants/moli: init overridetree for moli
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Patch Set 30: Code-Review+2
(1 comment)
File src/mainboard/google/brya/variants/moli/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62321/comment/d28ddffa_eab626e1
PS30, Line 67: 5 using clk
`PCIe 6 using clk 5`
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