coreboot-gerrit March 2022

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Change in coreboot[master]: ec/google: Add PSRC and PBOK method
by Varshit B Pandya (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Rizwan Qureshi, Tim Wawrzynczak, Eric Lai. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62945 ) Change subject: ec/google: Add PSRC and PBOK method ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62945/comment/5fcc211a_f6918282 PS1, Line 15: TEST=Buil, boot brya0 and dump SSDT to check methods > better to dump result here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia536a9e1528f6e415247eca9ed2b0b685eb73196 Gerrit-Change-Number: 62945 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 14:14:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/dptf: Add support for Power participant
by Varshit B Pandya (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Lance Zhao, Rizwan Qureshi, Tim Wawrzynczak, Eric Lai. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62944 ) Change subject: drivers/intel/dptf: Add support for Power participant ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62944/comment/f4cd547c_73c37fdd PS1, Line 13: TEST=Build, boot brya0 and dump SSDT to check TPWR device > could you post the acpi dump result here? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Gerrit-Change-Number: 62944 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 14:14:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/gumboz: Add fw_config probe for ALC5682-VD & VS
by Felix Held (Code Review) 21 Mar '22

21 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61782 ) Change subject: mb/google/zork/var/gumboz: Add fw_config probe for ALC5682-VD & VS ...................................................................... mb/google/zork/var/gumboz: Add fw_config probe for ALC5682-VD & VS ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:215292608 BRANCH=firmware-zork-13434.B TEST=ALC5682I-VS audio codec can work Change-Id: I0b0231a3ee9c0dad289ffd50607b3ae6201f56a0 Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61782 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-hsuan Hsu <yuhsuan(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/variants/gumboz/overridetree.cb 1 file changed, 87 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved Yu-hsuan Hsu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/zork/variants/gumboz/overridetree.cb b/src/mainboard/google/zork/variants/gumboz/overridetree.cb index d496de2..90677f5 100644 --- a/src/mainboard/google/zork/variants/gumboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/gumboz/overridetree.cb @@ -1,4 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later +fw_config + field AUDIO_CODEC_SOURCE 36 37 + option AUDIO_CODEC_ALC5682 0 + option AUDIO_CODEC_ALC5682I_VS 1 + end +end + chip soc/amd/picasso # Start : OPN Performance Configuration @@ -105,6 +112,86 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit + device pci 8.1 on + device pci 0.5 on + chip drivers/amd/i2s_machine_dev + register "hid" = ""AMDI5682"" + # DMIC select GPIO for ACP machine device + # This GPIO is used to select DMIC0 or DMIC1 by the + # kernel driver. It does not really have a polarity + # since low and high control the selection of DMIC and + # hence does not have an active polarity. + # Kernel driver does not use the polarity field and + # instead treats the GPIO selection as follows: + # Set low (0) = Select DMIC0 + # Set high (1) = Select DMIC1 + register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" + device generic 0.0 on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + end + chip drivers/amd/i2s_machine_dev + register "hid" = ""10029835"" + # DMIC select GPIO for ACP machine device + # This GPIO is used to select DMIC0 or DMIC1 by the + # kernel driver. It does not really have a polarity + # since low and high control the selection of DMIC and + # hence does not have an active polarity. + # Kernel driver does not use the polarity field and + # instead treats the GPIO selection as follows: + # Set low (0) = Select DMIC0 + # Set high (1) = Select DMIC1 + register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" + device generic 1.0 on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end + end + end # Audio + end + device pci 14.3 on + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)" + register "property_count" = "2" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" + device i2c 1a on end + end + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + device generic 1.0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)" + register "property_count" = "2" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" + device i2c 1a on end + end + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end + end + end + end + end end # domain device ref i2c_2 on -- To view, visit https://review.coreboot.org/c/coreboot/+/61782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b0231a3ee9c0dad289ffd50607b3ae6201f56a0 Gerrit-Change-Number: 61782 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/vell: Move WWAN devices for vell
by Felix Held (Code Review) 21 Mar '22

21 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62771 ) Change subject: mb/google/brya/vell: Move WWAN devices for vell ...................................................................... mb/google/brya/vell: Move WWAN devices for vell This was to merge PCIe ACPI code to WWAN device. Also, RTD3 devices are add to overridetree.cb where WWAN is present for vell. BUG=none BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62771 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 3af3164..6ffffcf 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -155,6 +155,31 @@ device generic 0 on end end end + device ref pcie_rp6 on + # Enable WWAN PCIE 6 using clk 5 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "reset_off_delay_ms" = "20" + register "srcclk_pin" = "5" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "skip_on_off_support" = "true" + device generic 0 alias rp6_rtd3 on end + end + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + register "add_acpi_dma_property" = "true" + use rp6_rtd3 as rtd3dev + device generic 0 on end + end + end device ref pcie_rp8 off end device ref pcie_rp9 off end device ref tcss_dma0 on 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b Gerrit-Change-Number: 62771 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google: Add PSRC and PBOK method
by Varshit B Pandya (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Rizwan Qureshi, Tim Wawrzynczak. Hello build bot (Jenkins), Rizwan Qureshi, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62945 to look at the new patch set (#2). Change subject: ec/google: Add PSRC and PBOK method ...................................................................... ec/google: Add PSRC and PBOK method As per Intel Dynamic Tuning revision 1.3.13 add support for PSRC and PBOK under \_SB.DPTF.TPWR device ec_fill_dptf_helpers() is used to generate all the helper function that DPTF requires. BUG=b:205928013 TEST=Buil, boot brya0 and dump SSDT to check methods Scope (\_SB.DPTF.TPWR) { Method (PSRC, 0, Serialized) { Local0 = \_SB.PCI0.LPCB.EC0.PWRT /* External reference */ Return ((Local0 && 0x0F)) } Method (PBOK, 1, Serialized) { Local0 = Arg0 Local0 &= 0x0F \_SB.PCI0.LPCB.EC0.PBOK = Local0 } } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: Ia536a9e1528f6e415247eca9ed2b0b685eb73196 --- M src/ec/google/chromeec/ec_dptf_helpers.c 1 file changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/62945/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia536a9e1528f6e415247eca9ed2b0b685eb73196 Gerrit-Change-Number: 62945 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/dptf: Add support for Power participant
by Varshit B Pandya (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Varshit B Pandya, Lance Zhao, Rizwan Qureshi, Tim Wawrzynczak. Hello Lance Zhao, build bot (Jenkins), Rizwan Qureshi, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62944 to look at the new patch set (#2). Change subject: drivers/intel/dptf: Add support for Power participant ...................................................................... drivers/intel/dptf: Add support for Power participant As per Intel Dynamic Tuning revision 1.3.13 add support for TPWR device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TPWR device Device (TPWR) { Name (_HID, "") // _HID: Hardware ID Name (_UID, "TPWR") // _UID: Unique ID Name (_STR, "Power Participant") // _STR: Description String Name (PTYP, 0x11) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/Kconfig M src/drivers/intel/dptf/dptf.c M src/drivers/intel/dptf/dptf.h M src/include/acpi/acpigen_dptf.h 5 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/62944/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Gerrit-Change-Number: 62944 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/adl-n: Add device ID for TCSS XHCI
by Maulik V Vaghela (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Krishna P Bhat D. Hello build bot (Jenkins), Subrata Banik, Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Krishna P Bhat D, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62955 to look at the new patch set (#5). Change subject: soc/intel/adl-n: Add device ID for TCSS XHCI ...................................................................... soc/intel/adl-n: Add device ID for TCSS XHCI This patch adds TCSS XHCI device ID for ADL-N CPU which is required for USB3 port enumeration. Document Reference: 645548 revision 1.0 (Chapter 2.3) BUG=None BRANCH=None TEST=Check if device is detected correctly and ACPI entries are generated for device 0d.0 Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/usb4/xhci.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/62955/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Gerrit-Change-Number: 62955 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Usha P <usha.p(a)intel.com> Gerrit-CC: harsha.b.r(a)intel.com Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
by Felix Held (Code Review) 21 Mar '22

21 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62904 ) Change subject: mb/google/brya: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR ...................................................................... mb/google/brya: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig which updates PMC settings in the IFD for Alder Lake A0 silicon. As Alder Lake A0 is intermediate stepping, and the IFD is locked in the production systems, so the Kconfig is deselected. BUG=b:190588098 BRANCH=firmware-brya-14505.B TEST=Build the coreboot for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I81fe7c792dd82d9d547d318ebda55ee4a0f3ac96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62904 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1d29b6f..199db11 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,6 +1,5 @@ config BOARD_GOOGLE_BRYA_COMMON def_bool n - select ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR select BOARD_ROMSIZE_KB_32768 select CR50_USE_LONG_INTERRUPT_PULSES select DRIVERS_GENERIC_ALC1015 -- To view, visit https://review.coreboot.org/c/coreboot/+/62904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81fe7c792dd82d9d547d318ebda55ee4a0f3ac96 Gerrit-Change-Number: 62904 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: rth
by Anshul Bansal (Code Review) 21 Mar '22

21 Mar '22

Anshul Bansal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62962 ) Change subject: rth ...................................................................... rth Reported-by: Bansal, Anshul <anshul.bansal(a)intel.com> Signed-off-by: Bansal, Anshul <anshul.bansal(a)intel.com> Change-Id: Icf4dfb915718096e6456b322526e987843fd1020 --- M 3rdparty/vboot A baseboard-brya-private M src/soc/intel/alderlake/fsp_params.c 3 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/62962/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 25b9493..22076b1 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 25b9493525325dfb5bc2c36321c43ec7665060fa +Subproject commit 22076b1036354be65ac694e3ed0657b6f344f9d1 diff --git a/baseboard-brya-private b/baseboard-brya-private new file mode 160000 index 0000000..c211c5a --- /dev/null +++ b/baseboard-brya-private @@ -0,0 +1 @@ +Subproject commit c211c5ac7efc4f9ef20ae638d056e18482cfde85 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 299d864..ee91958 100755 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -725,9 +725,6 @@ s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion; s_cfg->PchPmDisableEnergyReport = 0x0; s_cfg->RaceToHalt = 0x1; - s_cfg->ImonSlope[0] = 143; - s_cfg->ImonSlope[1] = 103; - s_cfg->VccInAuxImonSlope = 111; } static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/62962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf4dfb915718096e6456b322526e987843fd1020 Gerrit-Change-Number: 62962 Gerrit-PatchSet: 1 Gerrit-Owner: Anshul Bansal <anshul.bansal(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [offset, rth, and energy report]
by build bot (Jenkins) (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62961 ) Change subject: [offset, rth, and energy report] ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144358): https://review.coreboot.org/c/coreboot/+/62961/comment/68728387_27973875 PS1, Line 730: s_cfg->VccInAuxImonSlope = 111; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/62961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I332f0da1ec7257c80aefdce146d5dd8b44bf300c Gerrit-Change-Number: 62961 Gerrit-PatchSet: 1 Gerrit-Owner: Anshul Bansal <anshul.bansal(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 13:32:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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