coreboot-gerrit March 2022

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Change in coreboot[master]: soc/mediatek: Add timestamp to measure PERST# time
by Hung-Te Lin (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Angel Pons, Yu-Ping Wu, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62933 ) Change subject: soc/mediatek: Add timestamp to measure PERST# time ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/62933/comment/f1e0ae23_2dcdc732 PS1, Line 238: COLLECT_TIMESTAMPS > Since the 100ms delay is a requirement, should we always do this? If we just need one timer, what about using timer_monotonic_get , sowe don't need COLLECT_TIMESTAMPS? -- To view, visit https://review.coreboot.org/c/coreboot/+/62933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Gerrit-Change-Number: 62933 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 11:57:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
by Kevin Chang (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Subrata Banik, Peichao Wang, Kane Chen, Tim Wawrzynczak. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 ) Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s ...................................................................... Patch Set 7: (1 comment) This change is ready for review. File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/62919/comment/ede87e61_273f5908 PS2, Line 635: s_cfg->PcieRpAspm[i] = config->pcierpaspm[i]; > Hi Kane, […] Hi Kane and Subrata I had modify define to new method in latest patch, Is this method acceptable? -- To view, visit https://review.coreboot.org/c/coreboot/+/62919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Gerrit-Change-Number: 62919 Gerrit-PatchSet: 7 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 11:53:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Select VBOOT_MOCK_SECDATA for ADL-N
by Usha P (Code Review) 21 Mar '22

21 Mar '22

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62957 ) Change subject: mb/intel/adlrvp: Select VBOOT_MOCK_SECDATA for ADL-N ...................................................................... mb/intel/adlrvp: Select VBOOT_MOCK_SECDATA for ADL-N Use MOCK TPM in vboot, since TPM is not enabled in ADLN RVP. BRANCH:NONE TEST=build and boot ADL-N RVP. Verify no TPM errors in depthcharge. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: Ibc0112545dbd80921d89d48eff58c512729243af --- M src/mainboard/intel/adlrvp/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/62957/1 diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 927b8ed..0d32746 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -150,7 +150,7 @@ config VBOOT select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC + select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC -- To view, visit https://review.coreboot.org/c/coreboot/+/62957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc0112545dbd80921d89d48eff58c512729243af Gerrit-Change-Number: 62957 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/adl-n: Add device ID for TCSS XHCI
by Subrata Banik (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Maulik V Vaghela, Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Krishna P Bhat D. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62955 ) Change subject: soc/intel/adl-n: Add device ID for TCSS XHCI ...................................................................... Patch Set 3: (1 comment) File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/62955/comment/354a5eab_ca99aa38 PS3, Line 4134: 0x464e @Maulik, I don't see this ID in doc 645548 -- To view, visit https://review.coreboot.org/c/coreboot/+/62955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Gerrit-Change-Number: 62955 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Usha P <usha.p(a)intel.com> Gerrit-CC: harsha.b.r(a)intel.com Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 10:24:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl-n: Add device ID for TCSS XHCI
by Maulik V Vaghela (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Krishna P Bhat D. Hello build bot (Jenkins), Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Krishna P Bhat D, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62955 to look at the new patch set (#3). Change subject: soc/intel/adl-n: Add device ID for TCSS XHCI ...................................................................... soc/intel/adl-n: Add device ID for TCSS XHCI This patch adds TCSS XHCI device ID for ADL-N PCH which is required for USB3 port enumeration. Document Reference: 645548 (Chapter 2) BUG=None BRANCH=None TEST=Check if device is detected correctly and ACPI entries are generated for device 0d.0 Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/usb4/xhci.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/62955/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Gerrit-Change-Number: 62955 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Usha P <usha.p(a)intel.com> Gerrit-CC: harsha.b.r(a)intel.com Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/felwinter: Update DPTF parameters for Felwinter
by John Su (Code Review) 21 Mar '22

21 Mar '22

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62956 ) Change subject: mb/google/brya/var/felwinter: Update DPTF parameters for Felwinter ...................................................................... mb/google/brya/var/felwinter: Update DPTF parameters for Felwinter Follow thermal table from thermal team. Chang list: 1. Update CRT value for all sensors. 2. Update PSV value for all sensors. 3. Remove DPTF_CPU target from Active Policy. 4. Remove CPU target from Critical Policy. BUG=b:219690502 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I30d1133cd1a145300b035efb790bca606f608e4e --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 7 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/62956/1 diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index d184276..549b499 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -94,16 +94,6 @@ ## Active Policy register "policies.active" = "{ [0] = { - .target = DPTF_CPU, - .thresholds = { - TEMP_PCT(44, 76), - TEMP_PCT(40, 65), - TEMP_PCT(36, 53), - TEMP_PCT(32, 41), - TEMP_PCT(28, 29), - } - }, - [1] = { .target = DPTF_TEMP_SENSOR_1, .thresholds = { TEMP_PCT(44, 76), @@ -117,18 +107,17 @@ ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), - [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 70, 5000), }" ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), - [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 70, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), }" register "controls.power_limits" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/62956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30d1133cd1a145300b035efb790bca606f608e4e Gerrit-Change-Number: 62956 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Add timestamp to measure PERST# time
by Yu-Ping Wu (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Hung-Te Lin, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62933 ) Change subject: soc/mediatek: Add timestamp to measure PERST# time ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/cherry/bootblock.c: https://review.coreboot.org/c/coreboot/+/62933/comment/dae39320_fad1d982 PS1, Line 56: write64 We should also add read/write API for this in pcie_common.h. For example, void mtk_pcie_save_timestamp(uint64_t timestamp); uint64_t mtk_pcie_load_timestamp(void); File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/62933/comment/1d06eeef_0b9b9b5f PS1, Line 238: COLLECT_TIMESTAMPS Since the 100ms delay is a requirement, should we always do this? -- To view, visit https://review.coreboot.org/c/coreboot/+/62933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Gerrit-Change-Number: 62933 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 09:40:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl-n: Add device ID for TCSS XHCI
by Maulik V Vaghela (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Rizwan Qureshi, Krishna P Bhat D. Hello Rizwan Qureshi, Krishna P Bhat D, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62955 to look at the new patch set (#2). Change subject: soc/intel/adl-n: Add device ID for TCSS XHCI ...................................................................... soc/intel/adl-n: Add device ID for TCSS XHCI This patch adds TCSS XHCI device ID for ADL-N PCH which is required for USB3 port enumeration. BUG=None BRANCH=None TEST=Check if device is detected correctly and ACPI entries are generated for device 0d.0 Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/usb4/xhci.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/62955/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Gerrit-Change-Number: 62955 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Usha P <usha.p(a)intel.com> Gerrit-CC: harsha.b.r(a)intel.com Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/adl-n: Add device ID for TCSS XHCI
by Maulik V Vaghela (Code Review) 21 Mar '22

21 Mar '22

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62955 ) Change subject: soc/intel/adl-n: Add device ID for TCSS XHCI ...................................................................... soc/intel/adl-n: Add device ID for TCSS XHCI This patch adds TCSS XHCI device ID for ADL-N PCH which is required for USB3 port enumeration. BUG=None BRANCH=None TEST=Check if device is detected correctly and ACPI entries are generated for device 0d.0 Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/usb4/xhci.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/62955/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d1365f4..ff7d69a 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4131,6 +4131,7 @@ #define PCI_DID_INTEL_ADP_P_XHCI 0x51ed #define PCI_DID_INTEL_ADP_S_XHCI 0x7ae0 #define PCI_DID_INTEL_ADP_TCSS_XHCI 0x461e +#define PCI_DID_INTEL_ADP_N_TCSS_XHCI 0x464e #define PCI_DID_INTEL_ADP_M_XHCI 0x54ed #define PCI_DID_INTEL_MTL_XHCI 0x7e7d #define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0 diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c index 64e5601..20ed2a5 100644 --- a/src/soc/intel/common/block/usb4/xhci.c +++ b/src/soc/intel/common/block/usb4/xhci.c @@ -31,6 +31,7 @@ PCI_DID_INTEL_TGP_TCSS_XHCI, PCI_DID_INTEL_TGP_H_TCSS_XHCI, PCI_DID_INTEL_ADP_TCSS_XHCI, + PCI_DID_INTEL_ADP_N_TCSS_XHCI, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/62955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Gerrit-Change-Number: 62955 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mediatek/mt8186: Implement sdram_size() to get real dram size
by Yu-Ping Wu (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Hung-Te Lin, Xixi Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62065 ) Change subject: src/mediatek/mt8186: Implement sdram_size() to get real dram size ...................................................................... Patch Set 20: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62065/comment/1bf156a6_ad33ee3e PS20, Line 9: set to 4GB by default hard-coded to 4GB File src/soc/mediatek/mt8186/emi.c: https://review.coreboot.org/c/coreboot/+/62065/comment/e3af3768_43dbdb94 PS20, Line 28: channel = (void *)((uintptr_t)mc + sizeof(*mc)); Please fix this. -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 20 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 09:20:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2022