coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya/var/kinox: Modify DDR4 to non-interleaved
by Dtrain Hsu (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62953 to look at the new patch set (#2). Change subject: mb/google/brya/var/kinox: Modify DDR4 to non-interleaved ...................................................................... mb/google/brya/var/kinox: Modify DDR4 to non-interleaved Kinox is designed to 8-layer PCB. In order to reduce the length of memory singals, the DDR4 is designed from interleaved to non-interleaved. BUG=b:210094309 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e --- M src/mainboard/google/brya/variants/kinox/Makefile.inc A src/mainboard/google/brya/variants/kinox/memory.c 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/62953/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e Gerrit-Change-Number: 62953 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/kinox: Modify DDR4 to non-interleaved
by Dtrain Hsu (Code Review) 21 Mar '22

21 Mar '22

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62953 ) Change subject: mb/google/brya/var/kinox: Modify DDR4 to non-interleaved ...................................................................... mb/google/brya/var/kinox: Modify DDR4 to non-interleaved Kinox is designed to 8-layer PCB. In order to reduce the length of memory singals, the DDR4 is designed from interleaved to non-interleaved. BUG=b:210094309 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e --- M src/mainboard/google/brya/variants/kinox/Makefile.inc A src/mainboard/google/brya/variants/kinox/memory.c 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/62953/1 diff --git a/src/mainboard/google/brya/variants/kinox/Makefile.inc b/src/mainboard/google/brya/variants/kinox/Makefile.inc index 681c764..27174f4 100644 --- a/src/mainboard/google/brya/variants/kinox/Makefile.inc +++ b/src/mainboard/google/brya/variants/kinox/Makefile.inc @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c ramstage-y += gpio.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/kinox/memory.c b/src/mainboard/google/brya/variants/kinox/memory.c new file mode 100644 index 0000000..ad33e9c --- /dev/null +++ b/src/mainboard/google/brya/variants/kinox/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {50, 20, 25, 25, 25}, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .ddr_config = { + .dq_pins_interleaved = false, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &ddr4_mem_config; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e Gerrit-Change-Number: 62953 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: /mb/google/brya/var/taniks: Modify DPTF setting for taniks
by Joey Peng (Code Review) 21 Mar '22

21 Mar '22

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62952 ) Change subject: /mb/google/brya/var/taniks: Modify DPTF setting for taniks ...................................................................... /mb/google/brya/var/taniks: Modify DPTF setting for taniks Change settings according to thermal team test results BUG=b:215033682 TEST=build and tested on taniks board Change-Id: I567815782ece4ab7fcec7da6b787ee9eec27aba4 Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/variants/taniks/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/62952/1 diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index ddafa15..7b23d6e 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -137,7 +137,7 @@ [2] = { .target = DPTF_TEMP_SENSOR_2, .thresholds = { - TEMP_PCT(57, 40), + TEMP_PCT(57, 70), TEMP_PCT(54, 60), TEMP_PCT(48, 60), TEMP_PCT(45, 45), -- To view, visit https://review.coreboot.org/c/coreboot/+/62952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I567815782ece4ab7fcec7da6b787ee9eec27aba4 Gerrit-Change-Number: 62952 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/taeko: Enable Genesys L1 entry delay
by Kevin Chang (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Subrata Banik, Peichao Wang, Tim Wawrzynczak. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62918 ) Change subject: mb/google/brya/var/taeko: Enable Genesys L1 entry delay ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/brya/Kconfig.name: https://review.coreboot.org/c/coreboot/+/62918/comment/a4fa8ee6_3e0ff218 PS3, Line 139: select DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX > select DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX if DRIVERS_GENESYSLOGIC_GL9763E Update in latest patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/62918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I142a816611e204e6c8577d15b3f0a0e08251f848 Gerrit-Change-Number: 62918 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 06:48:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Save dram info to cbmem
by Xixi Chen (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Julius Werner, Yu-Ping Wu. Xixi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Save dram info to cbmem ...................................................................... Patch Set 26: (1 comment) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/61334/comment/2584ea16_09fba5c5 PS22, Line 123: p = (void *)((uintptr_t)mc + sizeof(*mc)); > > I still can't reproduce locally if I make x a global tbh […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 26 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 06:47:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Save dram info to cbmem
by Xixi Chen (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Julius Werner, Xixi Chen. Hello Xi Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61334 to look at the new patch set (#26). Change subject: soc/mediatek: Save dram info to cbmem ...................................................................... soc/mediatek: Save dram info to cbmem Store dram info in cbmem for payloads to use. BUG=b:206014043 TEST=Build pass on Kingler Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a --- M src/soc/mediatek/common/include/soc/emi.h M src/soc/mediatek/common/memory.c 2 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/61334/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 26 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload: Enable LTO by default
by Paul Menzel (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Nico Huber, Julius Werner. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51177 ) Change subject: libpayload: Enable LTO by default ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: It’d be great, if we could get this finally submitted. The last release was just tagged, so it’d give enough time for testing. -- To view, visit https://review.coreboot.org/c/coreboot/+/51177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bc58034ea8a9510ddc08d61d19e75a7c6f9cbc7 Gerrit-Change-Number: 51177 Gerrit-PatchSet: 11 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 06:38:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Enable LTO by default
by Paul Menzel (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Julius Werner. Paul Menzel has removed Furquan Shaikh from this change. ( https://review.coreboot.org/c/coreboot/+/51177 ) Change subject: libpayload: Enable LTO by default ...................................................................... Removed reviewer Furquan Shaikh. -- To view, visit https://review.coreboot.org/c/coreboot/+/51177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bc58034ea8a9510ddc08d61d19e75a7c6f9cbc7 Gerrit-Change-Number: 51177 Gerrit-PatchSet: 11 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/mtl: Do initial SoC commit till bootblock
by Subrata Banik (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Felix Singer, Jamie Ryu, Ethan Tsao, Ravishankar Sarawadi, Raj Astekar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62772 ) Change subject: soc/intel/mtl: Do initial SoC commit till bootblock ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: @Ravi, we have took AI (action item) from ADL upstream work that going forward, we will upstream both SOC and MB code together incrementally to avoid running into compilation issue. This way, we will always let the jenkin to build the SOC code against a mainboard. Hence, IMO, please support the incremental upstreaming, this is the feedback I wished to explain you during internal meeting, but unfortunately didn't get chance to pass this feedback. read the feedbacks and issue we have faced due to SoC code without a actual Mainboard in upstream https://review.coreboot.org/q/owner:subrata.banik%2540intel.com+topic:ADL_U… -- To view, visit https://review.coreboot.org/c/coreboot/+/62772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 Gerrit-Change-Number: 62772 Gerrit-PatchSet: 4 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 06:12:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: Add Intel common UFS code support
by Meera Ravindranath (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Daniil Lunev, Rizwan Qureshi. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62855 ) Change subject: soc/intel/common/block: Add Intel common UFS code support ...................................................................... Patch Set 2: (2 comments) File src/soc/intel/common/block/scs/ufs.c: https://review.coreboot.org/c/coreboot/+/62855/comment/ea4876a4_61bf6791 PS1, Line 16: PCI_DEVICE_ID_INTEL_ADP_UFS > When building from tot it compains this should be PCI_DID_INTEL_ADP_UFS Done https://review.coreboot.org/c/coreboot/+/62855/comment/fe4874a8_3c48d5bb PS1, Line 22: PCI_VENDOR_ID_INTEL > When building from tot it compains this should be PCI_VID_INTEL Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f034ced64e2eaef41a7807133361d74b5009d3 Gerrit-Change-Number: 62855 Gerrit-PatchSet: 2 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daniil Lunev <dlunev(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 05:47:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Daniil Lunev <dlunev(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit March 2022