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Change subject: mb/google: Remove unused cpu device
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
I can change to CR+2.
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Change subject: mb/google: Remove unused cpu device
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google: Remove unused cpu device
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Does anyone want to give CR+2? Julius?
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Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
......................................................................
Patch Set 3: Code-Review+1
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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62856/comment/073892a2_466e6c48
PS1, Line 619: s_cfg->UfsEnable[1] = 0;
> > As I commented on CB:62662 I don't understand whyt this is array and why we're using index 1 here. […]
Thanks Subrata, Yeah it's weird that we're enabling index 1 instead of 0. And whatever we do here we need some explanation in the comments as we did in CB:62914.
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Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
......................................................................
Patch Set 2:
(1 comment)
File src/drivers/intel/fsp2_0/fsp_timestamp.c:
https://review.coreboot.org/c/coreboot/+/62942/comment/7b93561c_1eb0f833
PS2, Line 101: memcpy((void *)rec, (uint8_t *)hdr + sizeof(struct fpdt_pei_ext_perf_header),
Since we're only reading data, can we avoid malloc/memcpy/free and just iterate over table?
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Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
If the name is unknown, is it possible to print guid instead?
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Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62942/comment/53e18846_befab0d0
PS2, Line 9: This patch enriches coreboot FSP2.0 driver to extract the FSP timestamp
: from FPDT (Firmware Performance Data Table) and display as part of
: ramstage boot stage if the SoC user selects the required
: `GET_FSP_TIMESTAMP` config.
Extracting this data sounds great. But instead of printing it to the CBMEM console, could you please add them to the CBMEM timestamp table?
Is the FSP data theoretically also accessible from the operating sytsem?
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Change subject: soc/intel/common: Configure TCSS access through IOE P2SB
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS9:
possible to split this cl into 2 parts
1. refactor the existing code
2. as ioe support
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