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Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62946 )
Change subject: ec/google: Notify DPTF driver power participant on PD event
......................................................................
ec/google: Notify DPTF driver power participant on PD event
The DPTF power participant device needs to be notified when
power source changes so it can re-evaluate power source and
power source change count, this can be later used by DPTF along
with methods provided by EC.
BUG=b:205928013
TEST=Build, boot brya0 and dump DSDT to check change
Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Change-Id: I07f58b928a0dba92bec3817177142c586e5014b9
---
M src/ec/google/chromeec/acpi/ec.asl
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/62946/1
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index 69d608b..c74b38f 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -15,6 +15,8 @@
External(\_SB.DPTC, MethodObj)
#endif
+External (\_SB.DPTF.TPWR, DeviceObj)
+
Device (EC0)
{
Name (_HID, EISAID ("PNP0C09"))
@@ -82,6 +84,8 @@
BTID, 8, // Battery index that host wants to read
USPP, 8, // USB Port Power
RFWU, 8, // Retimer Firmware Update
+ PWRT, 8, // Power source and change count
+ PBOK, 8, // Power source change count from dptf
}
#if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
@@ -352,6 +356,7 @@
{
Printf ("EC: GOT PD EVENT")
Notify (\_SB.PCI0.LPCB.EC0.CREC.ECPD, 0x80)
+ Notify (\_SB.DPTF.TPWR, 0x81)
}
#endif
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Hello build bot (Jenkins), Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62942
to look at the new patch set (#2).
Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
......................................................................
drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
This patch enriches coreboot FSP2.0 driver to extract the FSP timestamp
from FPDT (Firmware Performance Data Table) and display as part of
ramstage boot stage if the SoC user selects the required
`GET_FSP_TIMESTAMP` config.
The prerequisite to this implementation is to have FSP binary built with
`PcdFspPerformanceEnable` PCD set to `TRUE` to allow FSP to populate
the FPDT HOB.
BUG=b:216635831
TEST=Able to dump FSP performance data with GET_FSP_TIMESTAMP Kconfig
selected and met the FSP prerequisites.
+--------------------------------------------------+
|------ FSP Performance Timestamp Table Dump ------|
+--------------------------------------------------+
|Perf-ID Timestamp(ms) String/GUID |
+--------------------------------------------------+
0 460253 SEC
50 460263 PEI
40 460274 PreMem
1 495803 9b3ada4f-ae56-4c24-8deaf03b7558ae50
2 508959 9b3ada4f-ae56-4c24-8deaf03b7558ae50
1 515253 6141e486-7543-4f1a-a579ff532ed78e75
2 525453 6141e486-7543-4f1a-a579ff532ed78e75
1 532059 baeb5bee-5b33-480a-8ab7b29c85e7ceab
2 546806 baeb5bee-5b33-480a-8ab7b29c85e7ceab
1 553302 1b04374d-fa9c-420f-ac62fee6d45e8443
2 563859 1b04374d-fa9c-420f-ac62fee6d45e8443
1 569955 88c17e54-ebfe-4531-a992581029f58126
2 575753 88c17e54-ebfe-4531-a992581029f58126
1 582099 a8499e65-a6f6-48b0-96db45c266030d83
50f0 599599 unknown name
50f1 716649 unknown name
2 728507 a8499e65-a6f6-48b0-96db45c266030d83
1 734755 9e1cc850-6731-4848-87526673c7005eee
....
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/Makefile.inc
A src/drivers/intel/fsp2_0/fsp_timestamp.c
M src/drivers/intel/fsp2_0/include/fsp/util.h
4 files changed, 123 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/62942/2
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Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 )
Change subject: soc/mediatek: Save dram info to cbmem
......................................................................
Patch Set 25:
(1 comment)
File src/soc/mediatek/common/memory.c:
https://review.coreboot.org/c/coreboot/+/61334/comment/8716c6cd_50f82935
PS22, Line 123: p = (void *)((uintptr_t)mc + sizeof(*mc));
> I still can't reproduce locally if I make x a global tbh
I forgot to say, gcc option "-Os" is required to reproduce this. Try this with `gcc -Warray-bounds -Os test.c` inside CrOS SDK:
```
struct mystruct {
int b;
int c[0];
} d;
int main(void)
{
struct mystruct *p = &d;
p->c[0] = 123;
return 0;
}
```
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62772 )
Change subject: soc/intel/mtl: Do initial SoC commit till bootblock
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62772/comment/3d5dfd8d_e8468644
PS4, Line 9: List of changes:
Introduce the new device, and write *Meteor Lake* at least once?
https://review.coreboot.org/c/coreboot/+/62772/comment/90e4aa4a_cf13250d
PS4, Line 16:
Is the code all written from scratch?
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Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61020 )
Change subject: src/driver/wifi: Add _DSM method for DDRRFIM
......................................................................
Patch Set 21:
(1 comment)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/61020/comment/b7a8b871_eb5f730a
PS20, Line 539: dev = dev->link_list->children;
: const struct drivers_wifi_generic_config *config = dev->chip_info;
: if (dev) {
> child device should already be passed in to this function now if you rebase on master
Done
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