coreboot-gerrit March 2022

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Change in coreboot[master]: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
by Subrata Banik (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Ben Chuang, Tim Wawrzynczak, Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62917 ) Change subject: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E ...................................................................... Patch Set 3: (1 comment) File src/drivers/genesyslogic/gl9763e/gl9763e.c: https://review.coreboot.org/c/coreboot/+/62917/comment/5efa86a3_00e3c860 PS3, Line 27: { nit: you can drop this -- To view, visit https://review.coreboot.org/c/coreboot/+/62917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601 Gerrit-Change-Number: 62917 Gerrit-PatchSet: 3 Gerrit-Owner: Ben Chuang <benchuanggli(a)gmail.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lai Jason <jasonlai.genesyslogic(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ben Chuang <benchuanggli(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 05:15:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller
by Eric Lai (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi, Meera Ravindranath. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62856 ) Change subject: soc/intel/alderlake: Add support for UFS controller ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Copied my question here: This is define in eltherlake #define PCH_DEV_UFS0 _PCH_DEV(SIO0, 5) #define PCH_DEV_UFS1 _PCH_DEV(SIO0, 7) Icelake use 5 #define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5) Alderlake use 7 #define PCH_DEVFN_UFS _PCH_DEVFN(ISH, 7) If it's really port2, need Intel update the EDS and add some comment in the UPD. Per EDS, if only support 1 UFS should be index 0... -- To view, visit https://review.coreboot.org/c/coreboot/+/62856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 Gerrit-Change-Number: 62856 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 05:14:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
by Kane Chen (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Kevin Chang, Paul Menzel, Tim Wawrzynczak. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 ) Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/62919/comment/5c2451fe_f1ce11f4 PS2, Line 635: s_cfg->PcieRpAspm[i] = config->pcierpaspm[i]; by doing this, all projects without devicetree settings , PcieRpAspm will be 0. also , i don't understand why you need to control aspm on root port side. have you checked ASPM is working in OS? you should compare lspci -vvv on pcie device and root port -- To view, visit https://review.coreboot.org/c/coreboot/+/62919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Gerrit-Change-Number: 62919 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 04:40:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add support for exclusive IDs
by Karthik Ramasubramanian (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Robert Zieba, Raul Rangel, Reka Norman, Nick Vaccaro. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62905 ) Change subject: util/spd_tools: Add support for exclusive IDs ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 Gerrit-Change-Number: 62905 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 04:04:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: add delay time to rtd3-cold
by Terry Chen (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62949 to look at the new patch set (#3). Change subject: mb/google/brya/var/primus{4es}: add delay time to rtd3-cold ...................................................................... mb/google/brya/var/primus{4es}: add delay time to rtd3-cold This CL adds the delay time into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. BUG=b:224648680 Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0 --- M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/62949/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0 Gerrit-Change-Number: 62949 Gerrit-PatchSet: 3 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/corsola: Revise power-on sequence of PS8640
by Hung-Te Lin (Code Review) 21 Mar '22

21 Mar '22

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62893 ) Change subject: mb/google/corsola: Revise power-on sequence of PS8640 ...................................................................... mb/google/corsola: Revise power-on sequence of PS8640 Although the panel initializes fine and the fw recovery screen is displayed without issues, the current power-on sequence of the PS8640 violates the spec of the PS8640, which can be confirmed by measuring it with an oscilloscope. The sequence is: - set VDD12 to be 1.2V - set VDD33 to be 3.3V - pull hign PD# - pull down RST# - delay 2ms - pull high RST# - delay more than 50ms (55ms for margin) - pull down RST# - delay more than 50ms (55ms for margin) - pull high RST# This flow will increase 110ms if firmware display is enabled in krabby. For normal booting flow, the firmware will not be enabled, so it will meet boot time requirements of Chrome OS. (Less than 1s.) Datasheet name: PS8640_DS_V1.4_20200210.docx. Chapter: 14. BUG=b:222650141 TEST=show fw display normally in krabby. TEST=result of waveform meets the spec. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62893 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/display.c 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/corsola/display.c b/src/mainboard/google/corsola/display.c index fd269ec..48ab58e 100644 --- a/src/mainboard/google/corsola/display.c +++ b/src/mainboard/google/corsola/display.c @@ -19,6 +19,20 @@ /* Bridge functions */ static void bridge_ps8640_power_on(void) { + /* + * PS8640 power-on sequence is described in chapter 14, PS8640_DS_V1.4_20200210.docx + * - set VDD12 to be 1.2V + * - set VDD33 to be 3.3V + * - pull hign PD# + * - pull down RST# + * - delay 2ms + * - pull high RST# + * - delay more than 50ms (55ms for margin) + * - pull down RST# + * - delay more than 50ms (55ms for margin) + * - pull high RST# + */ + /* Set VRF12 to 1.2V and VCN33 to 3.3V */ mainboard_set_regulator_vol(MTK_REGULATOR_VRF12, 1200000); mainboard_set_regulator_vol(MTK_REGULATOR_VCN33, 3300000); @@ -29,6 +43,10 @@ gpio_output(GPIO_EDPBRDG_RST_L, 0); mdelay(2); gpio_output(GPIO_EDPBRDG_RST_L, 1); + mdelay(55); + gpio_output(GPIO_EDPBRDG_RST_L, 0); + mdelay(55); + gpio_output(GPIO_EDPBRDG_RST_L, 1); } static int bridge_ps8640_get_edid(u8 i2c_bus, struct edid *edid) -- To view, visit https://review.coreboot.org/c/coreboot/+/62893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3 Gerrit-Change-Number: 62893 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: add delay time for eMMC
by build bot (Jenkins) (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62949 ) Change subject: mb/google/brya/var/primus{4es}: add delay time for eMMC ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/brya/variants/primus/overridetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144331): https://review.coreboot.org/c/coreboot/+/62949/comment/de1b6f96_836ef943 PS1, Line 151: register "enable_delay_ms" = "20" trailing whitespace File src/mainboard/google/brya/variants/primus4es/overridetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144331): https://review.coreboot.org/c/coreboot/+/62949/comment/e652cc9a_c7a7e790 PS1, Line 145: register "enable_delay_ms" = "20" trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/62949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0 Gerrit-Change-Number: 62949 Gerrit-PatchSet: 1 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 03:08:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: add delay time for eMMC
by Terry Chen (Code Review) 21 Mar '22

21 Mar '22

Terry Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62949 ) Change subject: mb/google/brya/var/primus{4es}: add delay time for eMMC ...................................................................... mb/google/brya/var/primus{4es}: add delay time for eMMC BUG=b:224648680 Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0 --- M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/62949/1 diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 8832381..16a829b 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -147,6 +147,8 @@ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" register "srcclk_pin" = "6" + register "reset_delay_ms" = "50" + register "enable_delay_ms" = "20" device generic 0 alias emmc_rtd3 on end end # Enable PCIe-to-eMMC bridge PCIE 3 using clk 6 diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index 940c63f..0f184e3 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -141,6 +141,8 @@ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" register "srcclk_pin" = "6" + register "reset_delay_ms" = "50" + register "enable_delay_ms" = "20" device generic 0 alias emmc_rtd3 on end end # Enable PCIe-to-eMMC bridge PCIE 3 using clk 6 -- To view, visit https://review.coreboot.org/c/coreboot/+/62949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0 Gerrit-Change-Number: 62949 Gerrit-PatchSet: 1 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/corsola: Revise power-on sequence of PS8640
by Rex-BC Chen (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62893 ) Change subject: mb/google/corsola: Revise power-on sequence of PS8640 ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: @hung-te, could you help to merge this patch? Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/62893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3 Gerrit-Change-Number: 62893 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 02:52:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Add PCIe domain support
by Jianjun Wang (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Angel Pons. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62360 ) Change subject: mb/google/cherry: Add PCIe domain support ...................................................................... Patch Set 18: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62360/comment/3cb0ceae_989ed590 PS18, Line 9: Add override device tree for dojo and add PCIe domain support. > So not all variants of google/cherry are going to support PCIe? Yes, other platforms may support PCIe(e.g. wifi), but only dojo need NVMe boot, so it's the only platform that needs to work on coreboot stage. -- To view, visit https://review.coreboot.org/c/coreboot/+/62360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 Gerrit-Change-Number: 62360 Gerrit-PatchSet: 18 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 01:59:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit March 2022