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Change subject: [set offset, enable rth and energy report]
......................................................................
Patch Set 1:
(6 comments)
File src/soc/intel/alderlake/fsp_params.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144355):
https://review.coreboot.org/c/coreboot/+/62959/comment/8f0d05f0_9bc5eadb
PS1, Line 726:
trailing whitespace
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144355):
https://review.coreboot.org/c/coreboot/+/62959/comment/1388b107_03080f5c
PS1, Line 728: s_cfg->RaceToHalt = 0x1;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144355):
https://review.coreboot.org/c/coreboot/+/62959/comment/1a51faee_b1bc973c
PS1, Line 729: s_cfg->ImonSlope[0] = 143;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144355):
https://review.coreboot.org/c/coreboot/+/62959/comment/32ef7bc6_f46e1b6d
PS1, Line 730: s_cfg->ImonSlope[1] = 103;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144355):
https://review.coreboot.org/c/coreboot/+/62959/comment/e8dcb51d_0f04815b
PS1, Line 731: s_cfg->VccInAuxImonSlope = 111;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144355):
https://review.coreboot.org/c/coreboot/+/62959/comment/3d623030_9d6c4ecb
PS1, Line 733:
trailing whitespace
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Change subject: mb/google/brask/variants/moli: init overridetree for moli
......................................................................
Patch Set 28:
(1 comment)
Patchset:
PS27:
> i think we need to settle the FW_CONFIG bitmasks first otherwise LGTM
Ok,
I abandoned this CL, and squashed into CB:62852.
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Change subject: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support
......................................................................
Patch Set 3:
(3 comments)
File src/mainboard/clevo/tgl-u/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/62498/comment/a96be924_dc263ebb
PS1, Line 5: select BOARD_CLEVO_NV4X_BASE
> hmm, but that's exactly how it's done in clevo/cml-u/Kconfig{,. […]
I saw patches shifting these selects to the Kconfig.name to Kconfig files, e.g. CB:62816
Michał, let's apply it as well.
File src/mainboard/clevo/tgl-u/board.fmd:
PS1:
> Why is this needed?
Nothing special here. All handled automatically by build system. Michał you can remove the file.
File src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/62498/comment/f4c8adde_c245e156
PS1, Line 58: register "LpmStateDisableMask" = "
: LPM_S0i2_1 |
: LPM_S0i2_2 |
: LPM_S0i3_1 |
: LPM_S0i3_2 |
: LPM_S0i3_3 |
: LPM_S0i3_4
:
> well, this is already covered in src/soc/intel/tigerlake/lpm. […]
Yes, but it does not handle the LPM_S0i2_1. We can remove the rest I believe
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Change subject: soc/intel/adl-n: Add device ID for TCSS XHCI
......................................................................
Patch Set 4:
(1 comment)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/62955/comment/4f7fd4f1_ea41cabf
PS3, Line 4134: 0x464e
> Ah, okay, I had to download the latest revision.
Thank you for the review :)
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Change subject: drivers/pc80/tpm/tis.c: Use fixed TPM ACPI path
......................................................................
Patch Set 3: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62493/comment/21214e16_7fb4d150
PS1, Line 9: Windows 11 expect the TPM to reside under \\_SB_.PCI0 in ACPI device
: hierarchy, otherwise the TPM is not detected.
> Updated
Ack
https://review.coreboot.org/c/coreboot/+/62493/comment/c9bbd295_d8b1f2a8
PS1, Line 13: TEST=Boot Windows 11 on Clevo NV41MZ and see the TPm is detected
> No change on Linux, everything still works as expected.
Ack
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Change subject: soc/intel/adl-n: Add device ID for TCSS XHCI
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/intel/adl-n: Add device ID for TCSS XHCI
......................................................................
Patch Set 4:
(1 comment)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/62955/comment/bfb5ab38_3c1e9246
PS3, Line 4134: 0x464e
> Hi Subrata, […]
Ah, okay, I had to download the latest revision.
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Hello build bot (Jenkins), Subrata Banik, Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Krishna P Bhat D,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62955
to look at the new patch set (#4).
Change subject: soc/intel/adl-n: Add device ID for TCSS XHCI
......................................................................
soc/intel/adl-n: Add device ID for TCSS XHCI
This patch adds TCSS XHCI device ID for ADL-N PCH which is required
for USB3 port enumeration.
Document Reference: 645548 revision 1.0 (Chapter 2.3)
BUG=None
BRANCH=None
TEST=Check if device is detected correctly and ACPI entries are
generated for device 0d.0
Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/usb4/xhci.c
2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/62955/4
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Change subject: soc/intel/adl-n: Add device ID for TCSS XHCI
......................................................................
Patch Set 3:
(1 comment)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/62955/comment/2eba9674_011eeb48
PS3, Line 4134: 0x464e
> @Maulik, I don't see this ID in doc 645548
Hi Subrata,
Can you please tell me revision of the document? I was referring to revision 1.0
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