coreboot-gerrit March 2022

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Change in coreboot[master]: Documentation: Move documentation license to main menu
by Tim Wawrzynczak (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Felix Singer, Nico Huber, Patrick Georgi, Paul Menzel, Angel Pons, Michael Niewöhner, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62767 ) Change subject: Documentation: Move documentation license to main menu ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bfc4f52da8a93d78a62e3a68fd6f1dc8ae4d335 Gerrit-Change-Number: 62767 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 14:34:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google: Notify DPTF driver power participant on PD event
by Eric Lai (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Rizwan Qureshi, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62946 ) Change subject: ec/google: Notify DPTF driver power participant on PD event ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07f58b928a0dba92bec3817177142c586e5014b9 Gerrit-Change-Number: 62946 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 14:31:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google: Add PSRC and PBOK method
by Eric Lai (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Varshit B Pandya, Rizwan Qureshi, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62945 ) Change subject: ec/google: Add PSRC and PBOK method ...................................................................... Patch Set 2: (1 comment) File src/ec/google/chromeec/ec_dptf_helpers.c: https://review.coreboot.org/c/coreboot/+/62945/comment/4b9b27cb_7224a1c0 PS2, Line 134: static void write_power_pbok(const struct device *ec) so you can ARG0 & 0x0F then store to local0. -- To view, visit https://review.coreboot.org/c/coreboot/+/62945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia536a9e1528f6e415247eca9ed2b0b685eb73196 Gerrit-Change-Number: 62945 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 14:30:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/dptf: Add support for Power participant
by Eric Lai (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Varshit B Pandya, Lance Zhao, Rizwan Qureshi, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62944 ) Change subject: drivers/intel/dptf: Add support for Power participant ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Gerrit-Change-Number: 62944 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 14:28:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
by Kevin Chang (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Peichao Wang, Tim Wawrzynczak. Hello build bot (Jenkins), Peichao Wang, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62919 to look at the new patch set (#9). Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s ...................................................................... mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s GL9763e didn't support L0s state that disable L0s at root port. BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 --- M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 3 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/62919/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/62919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Gerrit-Change-Number: 62919 Gerrit-PatchSet: 9 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
by Kevin Chang (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Kevin Chang, Peichao Wang, Tim Wawrzynczak. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 ) Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s ...................................................................... Patch Set 8: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/62919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Gerrit-Change-Number: 62919 Gerrit-PatchSet: 8 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 21 Mar 2022 14:16:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/banshee: Add WiFi SAR table
by Felix Held (Code Review) 21 Mar '22

21 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62846 ) Change subject: mb/google/brya/var/banshee: Add WiFi SAR table ...................................................................... mb/google/brya/var/banshee: Add WiFi SAR table Add WiFi SAR table BUG=b:225285426 TEST=emerge-brya chromeos-config chromeos-config-bsp-private coreboot-private-files-baseboard-brya coreboot chromeos-bootimage and checked SAR table can load by WiFi driver. Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I8fa833409bd69e080fda735c89015b9548252190 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62846 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/banshee/Makefile.inc A src/mainboard/google/brya/variants/banshee/variant.c 3 files changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index e29ef9f..dd7935c 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -172,6 +172,7 @@ bool "-> Banshee" select BOARD_GOOGLE_BASEBOARD_BRYA select MEMORY_SODIMM + select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_CROTA bool "-> Crota" diff --git a/src/mainboard/google/brya/variants/banshee/Makefile.inc b/src/mainboard/google/brya/variants/banshee/Makefile.inc index 20c6c3c..3284196 100644 --- a/src/mainboard/google/brya/variants/banshee/Makefile.inc +++ b/src/mainboard/google/brya/variants/banshee/Makefile.inc @@ -3,3 +3,4 @@ romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/banshee/variant.c b/src/mainboard/google/brya/variants/banshee/variant.c new file mode 100644 index 0000000..6a79780 --- /dev/null +++ b/src/mainboard/google/brya/variants/banshee/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fa833409bd69e080fda735c89015b9548252190 Gerrit-Change-Number: 62846 Gerrit-PatchSet: 7 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add IOE P2SB for TCSS
by Felix Held (Code Review) 21 Mar '22

21 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62721 ) Change subject: soc/intel/common: Add IOE P2SB for TCSS ...................................................................... soc/intel/common: Add IOE P2SB for TCSS Meteor Lake has the IOE Die for TCSS. This change adds the IOE P2SB sideband access and exposes API for TCSS usage. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19 Signed-off-by: John Zhao <john.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62721 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/p2sb.h M src/soc/intel/common/block/p2sb/Kconfig M src/soc/intel/common/block/p2sb/Makefile.inc A src/soc/intel/common/block/p2sb/ioe_p2sb.c M src/soc/intel/common/block/p2sb/p2sb.c 5 files changed, 70 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index b330ccd..bf2fc67 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -29,6 +29,14 @@ void p2sb_enable_bar(void); void p2sb_configure_hpet(void); +/* + * Functions to access IOE P2SB. + * pid argument: SBI port Id + */ +void ioe_p2sb_enable_bar(void); +uint32_t ioe_p2sb_sbi_read(uint8_t pid, uint16_t reg); +void ioe_p2sb_sbi_write(uint8_t pid, uint16_t reg, uint32_t val); + union p2sb_bdf { struct { uint16_t fn : 3; diff --git a/src/soc/intel/common/block/p2sb/Kconfig b/src/soc/intel/common/block/p2sb/Kconfig index ff20255..e48baa5 100644 --- a/src/soc/intel/common/block/p2sb/Kconfig +++ b/src/soc/intel/common/block/p2sb/Kconfig @@ -9,3 +9,9 @@ select SOC_INTEL_COMMON_BLOCK_BASE_P2SB help Intel Processor common P2SB driver for PCH or SoC die + +config SOC_INTEL_COMMON_BLOCK_IOE_P2SB + bool + select SOC_INTEL_COMMON_BLOCK_BASE_P2SB + help + Intel Processor common P2SB driver for IOE die diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc index f051120..3274279 100644 --- a/src/soc/intel/common/block/p2sb/Makefile.inc +++ b/src/soc/intel/common/block/p2sb/Makefile.inc @@ -8,3 +8,9 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c + +# ioe_p2sb.c for IOE die P2SB IP +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOE_P2SB) += ioe_p2sb.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOE_P2SB) += ioe_p2sb.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOE_P2SB) += ioe_p2sb.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOE_P2SB) += ioe_p2sb.c diff --git a/src/soc/intel/common/block/p2sb/ioe_p2sb.c b/src/soc/intel/common/block/p2sb/ioe_p2sb.c new file mode 100644 index 0000000..85d8bc1 --- /dev/null +++ b/src/soc/intel/common/block/p2sb/ioe_p2sb.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/p2sb.h> +#include <intelblocks/p2sblib.h> +#include <intelblocks/pcr.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> + +uint32_t ioe_p2sb_sbi_read(uint8_t pid, uint16_t reg) +{ + return p2sb_dev_sbi_read(PCI_DEV_IOE_P2SB, pid, reg); +} + +void ioe_p2sb_sbi_write(uint8_t pid, uint16_t reg, uint32_t val) +{ + p2sb_dev_sbi_write(PCI_DEV_IOE_P2SB, pid, reg, val); +} + +void ioe_p2sb_enable_bar(void) +{ + p2sb_dev_enable_bar(PCI_DEV_IOE_P2SB, IOE_P2SB_BAR); +} + +static void read_resources(struct device *dev) +{ + mmio_resource(dev, 0, IOE_P2SB_BAR / KiB, IOE_P2SB_SIZE / KiB); +} + +struct device_operations device_ops = { + .read_resources = read_resources, + .set_resources = noop_set_resources, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_MTL_IOE_M_P2SB, + PCI_DID_INTEL_MTL_IOE_P_P2SB, + 0, +}; + +static const struct pci_driver ioe_p2sb __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 1b0c080..2517f69 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -139,8 +139,6 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_SOC_P2SB, - PCI_DID_INTEL_MTL_IOE_M_P2SB, - PCI_DID_INTEL_MTL_IOE_P_P2SB, PCI_DID_INTEL_APL_P2SB, PCI_DID_INTEL_GLK_P2SB, PCI_DID_INTEL_LWB_P2SB, -- To view, visit https://review.coreboot.org/c/coreboot/+/62721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19 Gerrit-Change-Number: 62721 Gerrit-PatchSet: 10 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google: Notify DPTF driver power participant on PD event
by Varshit B Pandya (Code Review) 21 Mar '22

21 Mar '22

Attention is currently required from: Rizwan Qureshi, Tim Wawrzynczak, Eric Lai. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62946 ) Change subject: ec/google: Notify DPTF driver power participant on PD event ...................................................................... Patch Set 2: (1 comment) File src/ec/google/chromeec/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/62946/comment/4d282c54_108c6160 PS1, Line 87: PWRT, 8, // Power source and change count > Are this need particular EC so support it? ACK, will comeback with the patch details for the corresponding change in EC -- To view, visit https://review.coreboot.org/c/coreboot/+/62946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07f58b928a0dba92bec3817177142c586e5014b9 Gerrit-Change-Number: 62946 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 21 Mar 2022 14:15:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/dirinboz: Add fw_config probe for ALC5682-VD & VS
by Felix Held (Code Review) 21 Mar '22

21 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61781 ) Change subject: mb/google/zork/var/dirinboz: Add fw_config probe for ALC5682-VD & VS ...................................................................... mb/google/zork/var/dirinboz: Add fw_config probe for ALC5682-VD & VS ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:211672259 BRANCH=firmware-zork-13434.B TEST=ALC5682I-VS audio codec can work Change-Id: Icd4321ec0a284e35511dd4b860a16506f54cf663 Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61781 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-hsuan Hsu <yuhsuan(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/variants/dirinboz/overridetree.cb 1 file changed, 87 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved Yu-hsuan Hsu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index d496de2..90677f5 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -1,4 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later +fw_config + field AUDIO_CODEC_SOURCE 36 37 + option AUDIO_CODEC_ALC5682 0 + option AUDIO_CODEC_ALC5682I_VS 1 + end +end + chip soc/amd/picasso # Start : OPN Performance Configuration @@ -105,6 +112,86 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit + device pci 8.1 on + device pci 0.5 on + chip drivers/amd/i2s_machine_dev + register "hid" = ""AMDI5682"" + # DMIC select GPIO for ACP machine device + # This GPIO is used to select DMIC0 or DMIC1 by the + # kernel driver. It does not really have a polarity + # since low and high control the selection of DMIC and + # hence does not have an active polarity. + # Kernel driver does not use the polarity field and + # instead treats the GPIO selection as follows: + # Set low (0) = Select DMIC0 + # Set high (1) = Select DMIC1 + register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" + device generic 0.0 on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + end + chip drivers/amd/i2s_machine_dev + register "hid" = ""10029835"" + # DMIC select GPIO for ACP machine device + # This GPIO is used to select DMIC0 or DMIC1 by the + # kernel driver. It does not really have a polarity + # since low and high control the selection of DMIC and + # hence does not have an active polarity. + # Kernel driver does not use the polarity field and + # instead treats the GPIO selection as follows: + # Set low (0) = Select DMIC0 + # Set high (1) = Select DMIC1 + register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" + device generic 1.0 on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end + end + end # Audio + end + device pci 14.3 on + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)" + register "property_count" = "2" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" + device i2c 1a on end + end + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + device generic 1.0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)" + register "property_count" = "2" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" + device i2c 1a on end + end + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end + end + end + end + end end # domain device ref i2c_2 on -- To view, visit https://review.coreboot.org/c/coreboot/+/61781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd4321ec0a284e35511dd4b860a16506f54cf663 Gerrit-Change-Number: 61781 Gerrit-PatchSet: 9 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: merged

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