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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/62963 )
Change subject: mb/google/guybrush: Update APCB file
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/blobs/+/62963/comment/aa534131_26d1ea7b
PS2, Line 9: is
Nit: not required.
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Change subject: mb/google/guybrush: Update APCB file
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS4:
> @subrata, are you suggesting SoC and MB bootblock ONLY code should compile and boot till last post code in bootblock?
if you can do that would be good.
> Does the current Make build supports only bootblock code compilation w/o other stages like romstage, ramstage ?
I believe coreboot supports state wise build.
The easiest part, would be add coreboot MB code with minimal skeleton alone that build start pointing to SoC Kconfig.
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Robert Zieba has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/62963 )
Change subject: mb/google/guybrush: Update APCB file
......................................................................
mb/google/guybrush: Update APCB file
The existing APCB file only has 4 SPD slots. This is will not be enough
for DeWatt devices due to upcoming changes in how RAM IDs are allocated
for that variant. This commit updates the APCB file to have enough
slots.
BUG=b:224884904
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: Ifbfe2c61c42cd503a70fd84c51ce184c40fed318
---
M mainboard/google/guybrush/APCB_CZN_D4.bin
1 file changed, 0 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/blobs refs/changes/63/62963/1
diff --git a/mainboard/google/guybrush/APCB_CZN_D4.bin b/mainboard/google/guybrush/APCB_CZN_D4.bin
index ff99c5d..3465e2e 100644
--- a/mainboard/google/guybrush/APCB_CZN_D4.bin
+++ b/mainboard/google/guybrush/APCB_CZN_D4.bin
Binary files differ
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Ravishankar Sarawadi has uploaded a new patch set (#5) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/62772 )
Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
......................................................................
soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
List of changes:
1. Add required Meteor Lake SoC programming till bootblock
2. Include only required headers into include/soc
3. Include MTL-P related DID, BDF
4. Ref: Processor EDS documents
vol1 #621483, vol2 #640858
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com>
Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4
---
A src/soc/intel/meteorlake/Kconfig
A src/soc/intel/meteorlake/Makefile.inc
A src/soc/intel/meteorlake/bootblock/bootblock.c
A src/soc/intel/meteorlake/bootblock/pch.c
A src/soc/intel/meteorlake/bootblock/report_platform.c
A src/soc/intel/meteorlake/include/soc/bootblock.h
A src/soc/intel/meteorlake/include/soc/espi.h
A src/soc/intel/meteorlake/include/soc/iomap.h
A src/soc/intel/meteorlake/include/soc/p2sb.h
A src/soc/intel/meteorlake/include/soc/pci_devs.h
A src/soc/intel/meteorlake/include/soc/pcr_ids.h
A src/soc/intel/meteorlake/include/soc/pm.h
A src/soc/intel/meteorlake/include/soc/smbus.h
13 files changed, 1,036 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62772/5
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Change subject: soc/intel/mtl: Do initial SoC commit till bootblock
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62772/comment/12602d2b_85e284c6
PS4, Line 9: List of changes:
> Introduce the new device, and write *Meteor Lake* at least once?
Ack
https://review.coreboot.org/c/coreboot/+/62772/comment/10ae9583_f3685979
PS4, Line 16:
> Is the code all written from scratch?
Meteor Lake SoC code including this bootblock stage code is based of Alder Lake.
Patchset:
PS4:
> @Ravi, we have took AI (action item) from ADL upstream work that going forward, we will upstream bot […]
@subrata, are you suggesting SoC and MB bootblock ONLY code should compile and boot till last post code in bootblock?
Does the current Make build supports only bootblock code compilation w/o other stages like romstage, ramstage ?
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Change subject: soc/intel/adl-n: Add device ID for TCSS XHCI
......................................................................
Patch Set 5: Code-Review+2
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Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62905 )
Change subject: util/spd_tools: Add support for exclusive IDs
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62905/comment/a10f149f_d33610b6
PS7, Line 12: have also have
> One *have* too many?
Done
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Hello build bot (Jenkins), Raul Rangel, Bhanu Prakash Maiya, Reka Norman, Nick Vaccaro, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62905
to look at the new patch set (#8).
Change subject: util/spd_tools: Add support for exclusive IDs
......................................................................
util/spd_tools: Add support for exclusive IDs
Currently memory parts that use the same SPD are assigned the same ID by
spd_tools. This commit adds support for exclusive IDs. When given an
exclusive ID a memory part will not share its ID with other parts unless
they also have the same exclusive ID.
BUG=b:225161910
TEST=Ran part_id_gen and checked that exclusive IDs work correctly and
that the current behavior still works in their abscence.
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8
---
M util/spd_tools/README.md
M util/spd_tools/src/part_id_gen/part_id_gen.go
2 files changed, 62 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/62905/8
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59638 )
Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
......................................................................
Patch Set 44:
(1 comment)
File src/drivers/intel/fsp2_0/include/fsp/util.h:
https://review.coreboot.org/c/coreboot/+/59638/comment/a1b1fa97_75da5e9a
PS44, Line 32: efi_physical_address
using uint64_t instead would make the data type size more obvious
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