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Change subject: soc/mediatek: Add early_init for passing data across sessions
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63019/comment/539049f2_2fe2ac9f
PS7, Line 9: ram stage
I think the spelling without space *ramstage* is more common in coreboot.
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Change subject: crossgcc: Upgrade LLVM from 13.0.1 to 14.0.0
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63123/comment/97eb471e_1896f66a
PS1, Line 8:
How did you test? QEMU boards?
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Change subject: mb/google/cherry: Pre-initialize PCIe at the bootblock stage
......................................................................
Patch Set 25:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62359/comment/3ccd49b9_4d0ea763
PS25, Line 13: wait
waiting
https://review.coreboot.org/c/coreboot/+/62359/comment/9e1aaf23_0c3ff6f6
PS25, Line 14: assert the pin in bootblock stage
… which is currently the only function of `mtk_pcie_pre_init()`, so …
https://review.coreboot.org/c/coreboot/+/62359/comment/81ee434c_c783ea87
PS25, Line 15: could be avoided
in romstage (or is it ramstage?) is avoided
Patchset:
PS25:
Jianjin, thank you very much for your patience and responsiveness. These change-sets evolved to a very good state.
File src/mainboard/google/cherry/bootblock.c:
https://review.coreboot.org/c/coreboot/+/62359/comment/bb834aff_2616bfb8
PS18, Line 48: mtk_pcie_pre_init();
> Ack
Hung-Te, out of curiousity, is it just taste or has it some technical reasons?
File src/mainboard/google/cherry/bootblock.c:
https://review.coreboot.org/c/coreboot/+/62359/comment/af26758a_5ee5835c
PS25, Line 49: mtk_pcie_pre_init
For me it’d be less confusing if the name of the function would be `mtk_pcie_assert_perst()`. Or a comment should be added, explaining why this function is called here.
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Change subject: mb/google/brya/{}: Add SBU orientation property for Type C Mux
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
Patchset:
PS6:
I tried this on:
- Anahera: Hotplugging a Type C display works with both orientations
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Change subject: amdfwtool: Add support for AMD's BIOS recovery feature
......................................................................
Patch Set 50:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/57131/comment/0f1d6583_a70bebe7
PS49, Line 1899: 0x20000
> should be the size of FW
The address here in UEFI image is hardcoded 0x20000. Do the same thing.
Done.
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Hello build bot (Jenkins), Zheng Bao,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#51).
Change subject: amdfwtool: Add support for AMD's BIOS recovery feature
......................................................................
amdfwtool: Add support for AMD's BIOS recovery feature
The BIOS recovery feature helps recover the computer from a Power On
Self-Test (POST) or a boot failure that is caused by a corrupt
BIOS. The system in BIOS recovery mode goes a different route, uses
different FWs and different AMD FW layout. So the amdfwtool needs to
change.
The addresses in PSP Level 1 and Level 2 point to same place.
Change-Id: I2671b95fe089aafdaf61b55bc9d2e8dcf6a66dbc
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
M util/amdfwtool/data_parse.c
3 files changed, 39 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/57131/51
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Change subject: amdfwtool: Add support for AMD's BIOS recovery feature
......................................................................
Patch Set 50:
(1 comment)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144796):
https://review.coreboot.org/c/coreboot/+/57131/comment/7e7b6ca7_a0e772ce
PS50, Line 1865: btl_entry = search_entry(pspdir2, AMD_FW_PSP_BOOTLOADER);
line over 96 characters
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Change subject: amdfwtool: Add support for AMD's BIOS recovery feature
......................................................................
Patch Set 49:
(3 comments)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/57131/comment/dd8e6a6e_e77f3c5f
PS49, Line 587: uint32_t index;
:
: index = 0;
> i'd combine those two lines into uint32_t index = 0;
Done
https://review.coreboot.org/c/coreboot/+/57131/comment/4685935d_603326e1
PS49, Line 592: break;
> you could do a return index instead of the break here and replace the if/else construct in lines 596 […]
Done
https://review.coreboot.org/c/coreboot/+/57131/comment/d0753226_795c0d3c
PS49, Line 1899: 0x20000
> should this be TABLE_ALIGNMENT?
should be the size of FW
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Hello build bot (Jenkins), Zheng Bao,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57131
to look at the new patch set (#50).
Change subject: amdfwtool: Add support for AMD's BIOS recovery feature
......................................................................
amdfwtool: Add support for AMD's BIOS recovery feature
The BIOS recovery feature helps recover the computer from a Power On
Self-Test (POST) or a boot failure that is caused by a corrupt
BIOS. The system in BIOS recovery mode goes a different route, uses
different FWs and different AMD FW layout. So the amdfwtool needs to
change.
Change-Id: I2671b95fe089aafdaf61b55bc9d2e8dcf6a66dbc
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
M util/amdfwtool/data_parse.c
3 files changed, 37 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/57131/50
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