coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: mb: add new board clevo/tgl-u/l140mu
by Michael Niewöhner (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Felix Singer, Paul Menzel, Tim Wawrzynczak. Hello Felix Singer, build bot (Jenkins), Paul Menzel, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59548 to look at the new patch set (#12). Change subject: mb: add new board clevo/tgl-u/l140mu ...................................................................... mb: add new board clevo/tgl-u/l140mu Add new board Clevo L14xMU (TGL). GPIOs were configured based on schematics. Tested and working: - On-board RAM (M471A1G44AB0-CWE) - DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1) - Graphics (GOP driver), including HDMI - Keyboard - I2C touchpad (including interrupt) - TPM (with interrupt on Windows, only polling on Linux [1]) - microSD Card reader - both NVME ports - Speakers - Microphone - Camera - WLAN/BT (CNVi) - All USB2/3 ports including Type-C - Thunderbolt detects my work laptop in TB Control Center (I couldn't test anything more due to security policy.) - TianoCore - internal flashing with flashrom Note on TPM: The vendor sets Intel PTT to default-on in newer CSME images, which conflicts with the dTPM. Currently, there are two ways to make it work: 1) Boot vendor firmware once to let it disable PTT via CSME firmware feature override. 2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to disabled. Boots fine: - Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6) - Windows 10 21H2 (Build 19044.1586) Untested: - Thunderbolt (see above) - Type-C DisplayPort - S-ATA - 3G/LTE - 3G/LTE depends on mising EC driver - tested board is non-LTE version with a second NVME port instead - LTE version has a USB-only M.2 slot (supported by this port) Doesn't work: - TPM interrupt on Linux [1] - WLAN/BT (PCIe) - gets detected but can't be enabled - All EC related functions - EC driver is WIP - Fn-Keys - S0ix - UCSI - Fan control - Battery info [1] https://lkml.org/lkml/2021/5/1/103 Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- A src/mainboard/clevo/tgl-u/Kconfig A src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/Makefile.inc A src/mainboard/clevo/tgl-u/board_info.txt A src/mainboard/clevo/tgl-u/bootblock.c A src/mainboard/clevo/tgl-u/cmos.default A src/mainboard/clevo/tgl-u/cmos.layout A src/mainboard/clevo/tgl-u/dsdt.asl A src/mainboard/clevo/tgl-u/include/variant/gpio.h A src/mainboard/clevo/tgl-u/include/variant/ramstage.h A src/mainboard/clevo/tgl-u/include/variant/romstage.h A src/mainboard/clevo/tgl-u/ramstage.c A src/mainboard/clevo/tgl-u/romstage.c A src/mainboard/clevo/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex A src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.inc A src/mainboard/clevo/tgl-u/variants/l140mu/board_info.txt A src/mainboard/clevo/tgl-u/variants/l140mu/data.vbt A src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb A src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c A src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c A src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c A src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c A src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c 23 files changed, 898 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/59548/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/59548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Gerrit-Change-Number: 59548 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb: add new board clevo/tgl-u/l140mu
by build bot (Jenkins) (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Felix Singer, Paul Menzel, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59548 ) Change subject: mb: add new board clevo/tgl-u/l140mu ...................................................................... Patch Set 11: (6 comments) File src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144800): https://review.coreboot.org/c/coreboot/+/59548/comment/f1e6424e_b0e727b6 PS11, Line 94: PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA / PCH_I2C_SDA (retimer rom) */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144800): https://review.coreboot.org/c/coreboot/+/59548/comment/aa920ad9_ab9ab1c1 PS11, Line 95: PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCL / PCH_I2C_SCL (retimer rom) */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144800): https://review.coreboot.org/c/coreboot/+/59548/comment/746de330_eee4dd0f PS11, Line 99: PAD_NC(GPP_C23, UP_20K), /* GPP_C23 / PCH_GPP_C23 (WLAN_WAKEUP#) */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144800): https://review.coreboot.org/c/coreboot/+/59548/comment/27dbf09a_3dd45945 PS11, Line 104: PAD_NC(GPP_D2, NONE), /* LEDKB_DET# (unused; not sold w/o KBLED) */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144800): https://review.coreboot.org/c/coreboot/+/59548/comment/08602d0c_17193d15 PS11, Line 107: PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# / SSD1_CLKREQ# (for SSD2!) */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144800): https://review.coreboot.org/c/coreboot/+/59548/comment/b6807453_19bb24e8 PS11, Line 110: PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# / SSD2_CLKREQ# (for SSD1!) */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/59548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Gerrit-Change-Number: 59548 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sat, 26 Mar 2022 17:48:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb: add new board clevo/tgl-u/l140mu
by Michael Niewöhner (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Felix Singer, Paul Menzel, Tim Wawrzynczak. Hello Felix Singer, build bot (Jenkins), Paul Menzel, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59548 to look at the new patch set (#11). Change subject: mb: add new board clevo/tgl-u/l140mu ...................................................................... mb: add new board clevo/tgl-u/l140mu Add new board Clevo L14xMU (TGL). GPIOs were configured based on schematics. Tested and working: - On-board RAM (M471A1G44AB0-CWE) - DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1) - Graphics (GOP driver), including HDMI - Keyboard - I2C touchpad (including interrupt) - TPM (with interrupt on Windows, only polling on Linux [1]) - microSD Card reader - both NVME ports - Speakers - Microphone - Camera - WLAN/BT (CNVi) - All USB2/3 ports including Type-C - Thunderbolt detects my work laptop in TB Control Center (I couldn't test anything more due to security policy.) - TianoCore - internal flashing with flashrom Note on TPM: The vendor sets Intel PTT to default-on in newer CSME images, which conflicts with the dTPM. Currently, there are two ways to make it work: 1) Boot vendor firmware once to let it disable PTT via CSME firmware feature override. 2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to disabled. Boots fine: - Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6) - Windows 10 21H2 (Build 19044.1586) Untested: - Thunderbolt (see above) - Type-C DisplayPort - S-ATA - 3G/LTE - 3G/LTE depends on mising EC driver - tested board is non-LTE version with a second NVME port instead - LTE version has a USB-only M.2 slot (supported by this port) Doesn't work: - TPM interrupt on Linux [1] - WLAN/BT (PCIe) - gets detected but can't be enabled - All EC related functions - EC driver is WIP - Fn-Keys - S0ix - UCSI - Fan control - Battery info [1] https://lkml.org/lkml/2021/5/1/103 Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- A src/mainboard/clevo/tgl-u/Kconfig A src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/Makefile.inc A src/mainboard/clevo/tgl-u/board_info.txt A src/mainboard/clevo/tgl-u/bootblock.c A src/mainboard/clevo/tgl-u/cmos.default A src/mainboard/clevo/tgl-u/cmos.layout A src/mainboard/clevo/tgl-u/dsdt.asl A src/mainboard/clevo/tgl-u/include/variant/gpio.h A src/mainboard/clevo/tgl-u/include/variant/ramstage.h A src/mainboard/clevo/tgl-u/include/variant/romstage.h A src/mainboard/clevo/tgl-u/ramstage.c A src/mainboard/clevo/tgl-u/romstage.c A src/mainboard/clevo/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex A src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.inc A src/mainboard/clevo/tgl-u/variants/l140mu/board_info.txt A src/mainboard/clevo/tgl-u/variants/l140mu/data.vbt A src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb A src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c A src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c A src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c A src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c A src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c 23 files changed, 899 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/59548/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/59548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Gerrit-Change-Number: 59548 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb: add new board clevo/tgl-u/l140mu
by build bot (Jenkins) (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Felix Singer, Paul Menzel, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59548 ) Change subject: mb: add new board clevo/tgl-u/l140mu ...................................................................... Patch Set 10: (6 comments) File src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144799): https://review.coreboot.org/c/coreboot/+/59548/comment/77b017fb_01552a32 PS10, Line 94: PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA / PCH_I2C_SDA (retimer rom) */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144799): https://review.coreboot.org/c/coreboot/+/59548/comment/d55797e6_ac341c43 PS10, Line 95: PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCL / PCH_I2C_SCL (retimer rom) */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144799): https://review.coreboot.org/c/coreboot/+/59548/comment/699afc80_11edee1b PS10, Line 99: PAD_NC(GPP_C23, UP_20K), /* GPP_C23 / PCH_GPP_C23 (WLAN_WAKEUP#) */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144799): https://review.coreboot.org/c/coreboot/+/59548/comment/5bfd2228_8a33c50d PS10, Line 104: PAD_NC(GPP_D2, NONE), /* LEDKB_DET# (unused; not sold w/o KBLED) */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144799): https://review.coreboot.org/c/coreboot/+/59548/comment/cf7537bb_f4230cd9 PS10, Line 107: PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# / SSD1_CLKREQ# (for SSD2!) */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144799): https://review.coreboot.org/c/coreboot/+/59548/comment/a440d1f8_ba14cccd PS10, Line 110: PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# / SSD2_CLKREQ# (for SSD1!) */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/59548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Gerrit-Change-Number: 59548 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sat, 26 Mar 2022 17:14:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb: add new board clevo/tgl-u/l140mu
by Michael Niewöhner (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Felix Singer, Paul Menzel, Tim Wawrzynczak. Hello Felix Singer, build bot (Jenkins), Paul Menzel, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59548 to look at the new patch set (#10). Change subject: mb: add new board clevo/tgl-u/l140mu ...................................................................... mb: add new board clevo/tgl-u/l140mu Add new board Clevo L14xMU (TGL). GPIOs were configured based on schematics. Tested and working: - On-board RAM (M471A1G44AB0-CWE) - DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1) - Graphics (GOP driver), including HDMI - Keyboard - I2C touchpad (including interrupt) - TPM (with interrupt on Windows, only polling on Linux [1]) - microSD Card reader - both NVME ports - Speakers - Microphone - Camera - WLAN/BT (CNVi) - All USB2/3 ports including Type-C - Thunderbolt detects my work laptop in TB Control Center (I couldn't test anything more due to security policy.) - TianoCore - internal flashing with flashrom Note on TPM: The vendor sets Intel PTT to default-on in newer CSME images, which conflicts with the dTPM. Currently, there are two ways to make it work: 1) Boot vendor firmware once to let it disable PTT via CSME firmware feature override. 2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to disabled. Boots fine: - Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6) - Windows 10 21H2 (Build 19044.1586) Untested: - Thunderbolt (see above) - Type-C DisplayPort - S-ATA - 3G/LTE - 3G/LTE depends on mising EC driver - tested board is non-LTE version with a second NVME port instead - LTE version has a USB-only M.2 slot (supported by this port) Doesn't work: - TPM interrupt on Linux [1] - WLAN/BT (PCIe) - gets detected but can't be enabled - All EC related functions - EC driver is WIP - Fn-Keys - S0ix - UCSI - Fan control - Battery info [1] https://lkml.org/lkml/2021/5/1/103 Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- A src/mainboard/clevo/tgl-u/Kconfig A src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/Makefile.inc A src/mainboard/clevo/tgl-u/board_info.txt A src/mainboard/clevo/tgl-u/bootblock.c A src/mainboard/clevo/tgl-u/cmos.default A src/mainboard/clevo/tgl-u/cmos.layout A src/mainboard/clevo/tgl-u/dsdt.asl A src/mainboard/clevo/tgl-u/include/variant/gpio.h A src/mainboard/clevo/tgl-u/include/variant/ramstage.h A src/mainboard/clevo/tgl-u/include/variant/romstage.h A src/mainboard/clevo/tgl-u/ramstage.c A src/mainboard/clevo/tgl-u/romstage.c A src/mainboard/clevo/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex A src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.inc A src/mainboard/clevo/tgl-u/variants/l140mu/board_info.txt A src/mainboard/clevo/tgl-u/variants/l140mu/data.vbt A src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb A src/mainboard/clevo/tgl-u/variants/l140mu/gma-mainboard.ads A src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c A src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c A src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c A src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c A src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c 24 files changed, 917 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/59548/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/59548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Gerrit-Change-Number: 59548 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: Makefile: Clean up old targets
by Elyes Haouas (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Arthur Heymans, Patrick Georgi, Martin Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63117 ) Change subject: Makefile: Clean up old targets ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccc62b3c54ee2a074c25674715403c1457f6aad3 Gerrit-Change-Number: 63117 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 26 Mar 2022 15:23:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values
by Elyes Haouas (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Arthur Heymans, Elyes Haouas. Hello build bot (Jenkins), Paul Menzel, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62647 to look at the new patch set (#3). Change subject: include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values ...................................................................... include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values Regarding JEDEC Standard No. 21-C, Release 30, page 13, DDR4_SPD_72B_SO_RDIMM and DDR4_SPD_72B_SO_UDIMM values are respectively 0x08 and 0x09. There is no affected board in coreboot tree. Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Id4e9c3814e2e7f379917bf93f7975af3aad31dbb --- M src/include/spd.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/62647/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4e9c3814e2e7f379917bf93f7975af3aad31dbb Gerrit-Change-Number: 62647 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/mediatek: Add timestamp to measure PERST# time
by Hung-Te Lin (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Rex-BC Chen, Paul Menzel, Angel Pons, Yu-Ping Wu, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62933 ) Change subject: soc/mediatek: Add timestamp to measure PERST# time ...................................................................... Patch Set 10: (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/62933/comment/9779d282_ad750480 PS10, Line 249: mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, true); > We should mdelay(100) in this case (and print a warning). no need to mdelay 100 - the perst_time_us (0) will sleep enough time later. -- To view, visit https://review.coreboot.org/c/coreboot/+/62933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Gerrit-Change-Number: 62933 Gerrit-PatchSet: 10 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 26 Mar 2022 14:58:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Add timestamp to measure PERST# time
by Yu-Ping Wu (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62933 ) Change subject: soc/mediatek: Add timestamp to measure PERST# time ...................................................................... Patch Set 10: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62933/comment/ea1eb095_430926c3 PS10, Line 7: Add timestamp to measure PERST# time Ensure PERST# deassertion time follows the spec https://review.coreboot.org/c/coreboot/+/62933/comment/985d5ec4_103870fd PS10, Line 9: Add timestamp support to measure the assertion time of PERST#. According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. To ensure the 100ms delay requirement is met, calculate the elapsed time since assertion. If it is smaller than 100ms, do an extra delay. File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/62933/comment/dd072b45_3384db34 PS3, Line 238: perst_time_us = mtk_pcie_perst_elapsed_time(); : printk(BIOS_DEBUG, "%s: %lld us elapsed since assert PERST#\n", : __func__, perst_time_us); : : /* : * Described in PCIe CEM specification sections 2.2 : * (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). : * The deassertion of PERST# should be delayed 100ms (TPVPERL) : * for the power and clock to become stable. : */ : if (perst_time_us < 100000) : printk(BIOS_WARNING, "%s: PERST# assert time %lld us may not enough for link up\n", : __func__, perst_time_us); : > Is that ok to use udelay()? Fine. File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/62933/comment/3eb1f98d_d894159c PS10, Line 249: mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, true); We should mdelay(100) in this case (and print a warning). https://review.coreboot.org/c/coreboot/+/62933/comment/d99e9d8f_4f03a786 PS10, Line 251: 100000 Add a local variable (maybe right above line#248) const uint64_t min_perst_time_us = 100000; /* 100 ms */ -- To view, visit https://review.coreboot.org/c/coreboot/+/62933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Gerrit-Change-Number: 62933 Gerrit-PatchSet: 10 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 26 Mar 2022 13:56:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/cherry: Pre-initialize PCIe at the bootblock stage
by Yu-Ping Wu (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Rex-BC Chen, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: mb/google/cherry: Pre-initialize PCIe at the bootblock stage ...................................................................... Patch Set 25: Code-Review+1 (1 comment) File src/mainboard/google/cherry/bootblock.c: https://review.coreboot.org/c/coreboot/+/62359/comment/f8a7d4b2_02e9722c PS25, Line 6: #include <soc/early_init.h> Do we need to include this? -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 25 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 26 Mar 2022 13:36:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022