coreboot-gerrit March 2022

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Change in coreboot[master]: soc/mediatek/mt8195: Add early init support
by Yu-Ping Wu (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Rex-BC Chen, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63020 ) Change subject: soc/mediatek/mt8195: Add early init support ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4eb7da53ff76c385cab18bbf84970e96b61662ac Gerrit-Change-Number: 63020 Gerrit-PatchSet: 7 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 26 Mar 2022 13:33:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Add PCIe domain support for dojo
by Yu-Ping Wu (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62360 ) Change subject: mb/google/cherry: Add PCIe domain support for dojo ...................................................................... Patch Set 21: (1 comment) Patchset: PS21: Since this is the patch that actually enables PCIe support, please move this to the end of the long CL chain. -- To view, visit https://review.coreboot.org/c/coreboot/+/62360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 Gerrit-Change-Number: 62360 Gerrit-PatchSet: 21 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 26 Mar 2022 13:31:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add early_init for passing data across sessions
by Yu-Ping Wu (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63019 ) Change subject: soc/mediatek: Add early_init for passing data across sessions ...................................................................... Patch Set 7: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63019/comment/ec795edf_1bf7642a PS7, Line 7: sessions stages https://review.coreboot.org/c/coreboot/+/63019/comment/c0d066da_60dcc3ea PS7, Line 9: Passing pcie timestamp from bootblock stage to ram stage, it can be used : for other modules if they needs to passing data across sessions. Add support for "early_init_data" region, which can be used to store data initialized in an early stage (such as bootblock), and retrieve it in later stages (such as ramstage). File src/soc/mediatek/common/early_init.c: https://review.coreboot.org/c/coreboot/+/63019/comment/5c979dbd_cd75cc8c PS7, Line 10: assert(sizeof(struct early_init_data) <= REGION_SIZE(early_init_data)); Does it compile if we use _Static_assert() in early_init.h? https://review.coreboot.org/c/coreboot/+/63019/comment/d120f0ee_65797b22 PS7, Line 16: init data https://review.coreboot.org/c/coreboot/+/63019/comment/7e90a380_9637c428 PS7, Line 26: init data https://review.coreboot.org/c/coreboot/+/63019/comment/d2eb2d29_992c5a56 PS7, Line 36: init data https://review.coreboot.org/c/coreboot/+/63019/comment/783b7cfd_2b1b1441 PS7, Line 44: was never done data was never saved File src/soc/mediatek/common/include/soc/early_init.h: https://review.coreboot.org/c/coreboot/+/63019/comment/3fa3b044_604c7a43 PS7, Line 19: saved_time init_time -- To view, visit https://review.coreboot.org/c/coreboot/+/63019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a Gerrit-Change-Number: 63019 Gerrit-PatchSet: 7 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 26 Mar 2022 13:30:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb: add new board clevo/tgl-u/l140mu
by Michael Niewöhner (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Felix Singer, Paul Menzel, Tim Wawrzynczak. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59548 ) Change subject: mb: add new board clevo/tgl-u/l140mu ...................................................................... Patch Set 9: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59548/comment/966bdee7_7ef69149 PS8, Line 12: - On-board RAM and DIMM slot > If you have the model numbers at hand, that’d be great to have documented. Ack https://review.coreboot.org/c/coreboot/+/59548/comment/6af14de9_94046f9a PS8, Line 25: I couldn't test anything more due to security policy > Dot/period at the end. Done https://review.coreboot.org/c/coreboot/+/59548/comment/4e93461a_f3799aeb PS8, Line 26: TianoCore > The one from Kconfig, that means MrChromebox’ version? yes, Kconfig default https://review.coreboot.org/c/coreboot/+/59548/comment/fe00c43d_63e94615 PS8, Line 27: > How did you figure out the GPIOs? inteltool? Ack https://review.coreboot.org/c/coreboot/+/59548/comment/0bf7fedf_c94113a9 PS8, Line 48: - TPM interrupt on Linux [1] > Probably that took a large chunk of time to figure out. […] It took me two evenings \o/ In the end I've been debugging in uefishell manually configuring and sending commands via `mm` to find out if the GPIO works at all. Since Linux' tpm_tis driver is a mess, it took some time to find out what's going wrong there... The main problems are: - locality request missing, thus global INT_EN never gets set - interrupt test could *never* work bc it's simply broken and obviously was never tested before committing https://review.coreboot.org/c/coreboot/+/59548/comment/7ffdec8e_478870a3 PS8, Line 56: > It’d be great, if you also added, if flashrom’s internal programmer works with the vendor firmware, […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Gerrit-Change-Number: 59548 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sat, 26 Mar 2022 12:38:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb: add new board clevo/tgl-u/l140mu
by Michael Niewöhner (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Felix Singer, Paul Menzel, Tim Wawrzynczak. Hello Felix Singer, build bot (Jenkins), Paul Menzel, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59548 to look at the new patch set (#9). Change subject: mb: add new board clevo/tgl-u/l140mu ...................................................................... mb: add new board clevo/tgl-u/l140mu Add new board Clevo L14xMU (TGL). GPIOs were configured based on schematics. Tested and working: - On-board RAM (M471A1G44AB0-CWE) - DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1) - Graphics (GOP driver), including HDMI - Keyboard - I2C touchpad (including interrupt) - TPM (with interrupt on Windows, only polling on Linux [1]) - microSD Card reader - both NVME ports - Speakers - Microphone - Camera - WLAN/BT (CNVi) - All USB2/3 ports including Type-C - Thunderbolt detects my work laptop in TB Control Center (I couldn't test anything more due to security policy.) - TianoCore - internal flashing with flashrom Note on TPM: The vendor sets Intel PTT to default-on in newer CSME images, which conflicts with the dTPM. Currently, there are two ways to make it work: 1) Boot vendor firmware once to let it disable PTT via CSME firmware feature override. 2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to disabled. Boots fine: - Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6) - Windows 10 21H2 (Build 19044.1586) Untested: - Thunderbolt (see above) - Type-C DisplayPort - S-ATA - 3G/LTE - 3G/LTE depends on mising EC driver - tested board is non-LTE version with a second NVME port instead - LTE version has a USB-only M.2 slot (supported by this port) Doesn't work: - TPM interrupt on Linux [1] - WLAN/BT (PCIe) - gets detected but can't be enabled - All EC related functions - EC driver is WIP - Fn-Keys - S0ix - UCSI - Fan control - Battery info [1] https://lkml.org/lkml/2021/5/1/103 Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- A src/mainboard/clevo/tgl-u/Kconfig A src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/Makefile.inc A src/mainboard/clevo/tgl-u/board_info.txt A src/mainboard/clevo/tgl-u/bootblock.c A src/mainboard/clevo/tgl-u/cmos.default A src/mainboard/clevo/tgl-u/cmos.layout A src/mainboard/clevo/tgl-u/dsdt.asl A src/mainboard/clevo/tgl-u/include/variant/gpio.h A src/mainboard/clevo/tgl-u/include/variant/ramstage.h A src/mainboard/clevo/tgl-u/include/variant/romstage.h A src/mainboard/clevo/tgl-u/ramstage.c A src/mainboard/clevo/tgl-u/romstage.c A src/mainboard/clevo/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex A src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.inc A src/mainboard/clevo/tgl-u/variants/l140mu/board_info.txt A src/mainboard/clevo/tgl-u/variants/l140mu/data.vbt A src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb A src/mainboard/clevo/tgl-u/variants/l140mu/gma-mainboard.ads A src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c A src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c A src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c A src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c A src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c 24 files changed, 917 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/59548/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/59548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Gerrit-Change-Number: 59548 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/lpc: Add support to not clear port80 enable
by Paul Menzel (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63118 ) Change subject: soc/amd/common/block/lpc: Add support to not clear port80 enable ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63118/comment/2d44d081_96a4d0fa PS2, Line 12: Are AMD’s SMU folks aware of that problem? -- To view, visit https://review.coreboot.org/c/coreboot/+/63118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 Gerrit-Change-Number: 63118 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 26 Mar 2022 09:59:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina: Donot clear Port80 enable bit in ESPI Decode
by Paul Menzel (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63122 ) Change subject: soc/amd/sabrina: Donot clear Port80 enable bit in ESPI Decode ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63122/comment/e1a91eb4_5ef0b854 PS1, Line 8: Why? What problem does it fix, and where is that documented? -- To view, visit https://review.coreboot.org/c/coreboot/+/63122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae Gerrit-Change-Number: 63122 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 26 Mar 2022 09:58:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Disable PSP postcodes
by Paul Menzel (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63119 ) Change subject: mb/google/skyrim: Disable PSP postcodes ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63119/comment/f653889d_3698c9e2 PS3, Line 8: Why? -- To view, visit https://review.coreboot.org/c/coreboot/+/63119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22 Gerrit-Change-Number: 63119 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 26 Mar 2022 09:58:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values
by Paul Menzel (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Arthur Heymans, Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62647 ) Change subject: include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: > non, there is no affected board in coreboot tree. Maybe add that to the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/62647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4e9c3814e2e7f379917bf93f7975af3aad31dbb Gerrit-Change-Number: 62647 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 26 Mar 2022 09:56:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in coreboot[master]: mb: add new board clevo/tgl-u/l140mu
by Paul Menzel (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Felix Singer, Tim Wawrzynczak, Michael Niewöhner. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59548 ) Change subject: mb: add new board clevo/tgl-u/l140mu ...................................................................... Patch Set 8: Code-Review+1 (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59548/comment/f1b162a4_68f01d55 PS8, Line 12: - On-board RAM and DIMM slot If you have the model numbers at hand, that’d be great to have documented. https://review.coreboot.org/c/coreboot/+/59548/comment/d9b682b9_3d32fd1a PS8, Line 25: I couldn't test anything more due to security policy Dot/period at the end. https://review.coreboot.org/c/coreboot/+/59548/comment/4c3ae4f7_96aa91e9 PS8, Line 26: TianoCore The one from Kconfig, that means MrChromebox’ version? https://review.coreboot.org/c/coreboot/+/59548/comment/b8a9ef61_528d62ce PS8, Line 27: How did you figure out the GPIOs? inteltool? https://review.coreboot.org/c/coreboot/+/59548/comment/bc2c9117_9b61a425 PS8, Line 48: - TPM interrupt on Linux [1] Probably that took a large chunk of time to figure out. Hopefully not more than making the actual coreboot port. https://review.coreboot.org/c/coreboot/+/59548/comment/f8a91d26_1aa8be34 PS8, Line 56: It’d be great, if you also added, if flashrom’s internal programmer works with the vendor firmware, so coreboot can be written to the BIOS region. Patchset: PS8: Awesome stuff. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/59548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Gerrit-Change-Number: 59548 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Sat, 26 Mar 2022 09:55:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2022