coreboot-gerrit March 2022

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Change in coreboot[master]: soc/mediatek: Add timestamp to measure PERST# time
by Jianjun Wang (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel, Angel Pons, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Rex-BC Chen, Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62933 to look at the new patch set (#10). Change subject: soc/mediatek: Add timestamp to measure PERST# time ...................................................................... soc/mediatek: Add timestamp to measure PERST# time Add timestamp support to measure the assertion time of PERST#. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the measured PERST# time: [DEBUG] mtk_pcie_domain_enable: 432517 us elapsed since assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (17 tries) And the SSD information in boot log is as follows: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 --- M src/soc/mediatek/common/pcie.c M src/soc/mediatek/mt8195/pcie.c 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/62933/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/62933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Gerrit-Change-Number: 62933 Gerrit-PatchSet: 10 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/cherry: Pre-initialize PCIe at the bootblock stage
by Jianjun Wang (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Rex-BC Chen, Angel Pons. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Paul Menzel, Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62359 to look at the new patch set (#25). Change subject: mb/google/cherry: Pre-initialize PCIe at the bootblock stage ...................................................................... mb/google/cherry: Pre-initialize PCIe at the bootblock stage Described in PCIe CEM specification sections 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Instead of asserting PERST# right before PCIe initialization and wait for 100ms, assert the pin in bootblock stage so that the extra 100ms delay could be avoided. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d --- M src/mainboard/google/cherry/bootblock.c M src/soc/mediatek/mt8195/Makefile.inc 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/62359/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 25 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: Add early init support
by Jianjun Wang (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Rex-BC Chen, Angel Pons, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Rex-BC Chen, Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63020 to look at the new patch set (#7). Change subject: soc/mediatek/mt8195: Add early init support ...................................................................... soc/mediatek/mt8195: Add early init support Add early init support for MT8195 platform. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I4eb7da53ff76c385cab18bbf84970e96b61662ac --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/bootblock.c M src/soc/mediatek/mt8195/include/soc/memlayout.ld 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/63020/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4eb7da53ff76c385cab18bbf84970e96b61662ac Gerrit-Change-Number: 63020 Gerrit-PatchSet: 7 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Add early_init for passing data across sessions
by Jianjun Wang (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Rex-BC Chen, Paul Menzel, Angel Pons, Jianjun Wang. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Paul Menzel, Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63019 to look at the new patch set (#7). Change subject: soc/mediatek: Add early_init for passing data across sessions ...................................................................... soc/mediatek: Add early_init for passing data across sessions Passing pcie timestamp from bootblock stage to ram stage, it can be used for other modules if they needs to passing data across sessions. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a --- A src/soc/mediatek/common/early_init.c A src/soc/mediatek/common/include/soc/early_init.h 2 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63019/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a Gerrit-Change-Number: 63019 Gerrit-PatchSet: 7 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Add early_init for passing data across sessions
by Yu-Ping Wu (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Rex-BC Chen, Paul Menzel, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63019 ) Change subject: soc/mediatek: Add early_init for passing data across sessions ...................................................................... Patch Set 6: (3 comments) File src/soc/mediatek/common/include/soc/early_init.h: https://review.coreboot.org/c/coreboot/+/63019/comment/48e84e9b_699bf806 PS6, Line 18: struct early_init { early_init_data https://review.coreboot.org/c/coreboot/+/63019/comment/db812ebf_9b38db93 PS6, Line 23: void early_init_save_timestamp(enum early_init_type init_type); ...save_time https://review.coreboot.org/c/coreboot/+/63019/comment/2461d157_cbc688ac PS6, Line 24: uint64_t early_init_get_elapsed_time(enum early_init_type init_type); ..._us -- To view, visit https://review.coreboot.org/c/coreboot/+/63019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a Gerrit-Change-Number: 63019 Gerrit-PatchSet: 6 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 26 Mar 2022 07:38:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: crossgcc: Upgrade LLVM from 13.0.1 to 14.0.0
by Elyes Haouas (Code Review) 26 Mar '22

26 Mar '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63123 ) Change subject: crossgcc: Upgrade LLVM from 13.0.1 to 14.0.0 ...................................................................... crossgcc: Upgrade LLVM from 13.0.1 to 14.0.0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I3613522fa2a958d2a42674f17aa794bdda4ca74a --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-13.0.1.src.tar.xz.cksum A util/crossgcc/sum/clang-14.0.0.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-13.0.1.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-14.0.0.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-13.0.1.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-14.0.0.src.tar.xz.cksum D util/crossgcc/sum/llvm-13.0.1.src.tar.xz.cksum A util/crossgcc/sum/llvm-14.0.0.src.tar.xz.cksum 9 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/63123/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 6b7558f..c2aca7e 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -39,7 +39,7 @@ BINUTILS_VERSION=2.37 IASL_VERSION=20211217 # CLANG version number -CLANG_VERSION=13.0.1 +CLANG_VERSION=14.0.0 CMAKE_VERSION=3.22.2 NASM_VERSION=2.15.05 diff --git a/util/crossgcc/sum/clang-13.0.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-13.0.1.src.tar.xz.cksum deleted file mode 100644 index e7393a4..0000000 --- a/util/crossgcc/sum/clang-13.0.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -9cdc305550fbd27d52d023e8506c50c41e97b7fa tarballs/clang-13.0.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-14.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-14.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..b1899e6 --- /dev/null +++ b/util/crossgcc/sum/clang-14.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +517d56ccc605a9f180266f8fbe742599d743b82a tarballs/clang-14.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-13.0.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-13.0.1.src.tar.xz.cksum deleted file mode 100644 index 80c882a..0000000 --- a/util/crossgcc/sum/clang-tools-extra-13.0.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -ee28b71609e57e677205f44076e450fe5f577a22 tarballs/clang-tools-extra-13.0.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-14.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-14.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..2ce2ec8 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-14.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +676c15c96fece5bdf7ed5eaf08f6f4c1ecfa8898 tarballs/clang-tools-extra-14.0.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-13.0.1.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-13.0.1.src.tar.xz.cksum deleted file mode 100644 index 51cf82f..0000000 --- a/util/crossgcc/sum/compiler-rt-13.0.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -68e9e2f569ccfe0af9f5df61ec74808688198946 tarballs/compiler-rt-13.0.1.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-14.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-14.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..dfe93e6 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-14.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +6e285bfcbd93160355011a276efec3112d3179f2 tarballs/compiler-rt-14.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-13.0.1.src.tar.xz.cksum b/util/crossgcc/sum/llvm-13.0.1.src.tar.xz.cksum deleted file mode 100644 index 6f34362..0000000 --- a/util/crossgcc/sum/llvm-13.0.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -8e50e3e47b6a14a0848862c574fb0007db212482 tarballs/llvm-13.0.1.src.tar.xz diff --git a/util/crossgcc/sum/llvm-14.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-14.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..463ee75 --- /dev/null +++ b/util/crossgcc/sum/llvm-14.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +e56aad75fe66a33cb027464099c8164605693c49 tarballs/llvm-14.0.0.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/63123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3613522fa2a958d2a42674f17aa794bdda4ca74a Gerrit-Change-Number: 63123 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Add early_init for passing data across sessions
by Hung-Te Lin (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Rex-BC Chen, Paul Menzel, Angel Pons, Yu-Ping Wu, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63019 ) Change subject: soc/mediatek: Add early_init for passing data across sessions ...................................................................... Patch Set 6: (1 comment) File src/soc/mediatek/common/Kconfig: https://review.coreboot.org/c/coreboot/+/63019/comment/66f8a37d_22d9ab24 PS1, Line 53: config MEDIATEK_EARLY_INIT : bool : help : This option allows passing data across sessions. > hungte? Currently the common/* is added into build rules from SoC folder Makefile, so I think it's still easy to "only +early_init.c for platforms having early init in the memlayout.ld". Unless if we'll be sharing a module, for example PCIe, for multiple platforms that only some of them will do early_init. I still think we don't need EARLY_INIT to be a config, unless if you really see build failure (in fact, I'm even considering to add early_init to old platforms if we start adding non-pcie fields to them). -- To view, visit https://review.coreboot.org/c/coreboot/+/63019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a Gerrit-Change-Number: 63019 Gerrit-PatchSet: 6 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 26 Mar 2022 07:19:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82801gx/azalia.c: Fix read on 16-bit register
by Elyes Haouas (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Paul Menzel, Angel Pons, Arthur Heymans, Patrick Rudolph. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61845 ) Change subject: sb/intel/i82801gx/azalia.c: Fix read on 16-bit register ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: ping :) -- To view, visit https://review.coreboot.org/c/coreboot/+/61845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I530aa21d5a26ade0bc071351ac609c84bd8eb2cb Gerrit-Change-Number: 61845 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 26 Mar 2022 07:17:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src: Drop unused Kconfig symbols
by Elyes Haouas (Code Review) 26 Mar '22

26 Mar '22

Attention is currently required from: Lance Zhao, Paul Menzel, Tim Wawrzynczak, Arthur Heymans, Patrick Rudolph, Felix Held. Hello Felix Singer, Erik van den Bogaert, Lance Zhao, build bot (Jenkins), Frans Hendriks, Paul Menzel, Tim Wawrzynczak, Patrick Rudolph, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62362 to look at the new patch set (#10). Change subject: src: Drop unused Kconfig symbols ...................................................................... src: Drop unused Kconfig symbols Remove following unused symbols: SMM_STUB_STACK_SIZE HAVE_DEBUG_CAR DEBUG_CAR UART_USE_REFCLK_AS_INPUT_CLOCK ONBOARD_SAMSUNG_MEM ONBOARD_MEM_SAMSUNG NUM_OF_IOAPICS SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB SOC_INTEL_COMMON_BLOCK_SMBUS_ACPI_DRIVER Change-Id: I96380d4567356c81e17de469fd78cec2fcb7e5c9 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/cpu/x86/Kconfig M src/cpu/x86/Kconfig.debug_cpu M src/drivers/uart/Kconfig M src/mainboard/facebook/fbg1701/Kconfig M src/mainboard/portwell/m107/Kconfig M src/northbridge/amd/pi/Kconfig M src/soc/intel/common/block/sgx/Kconfig M src/soc/intel/common/block/smbus/Kconfig 8 files changed, 0 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/62362/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/62362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96380d4567356c81e17de469fd78cec2fcb7e5c9 Gerrit-Change-Number: 62362 Gerrit-PatchSet: 10 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device: Demote missing set resources message from error to warnings
by Terry Chen (Code Review) 26 Mar '22

26 Mar '22

Terry Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/63078 ) Change subject: device: Demote missing set resources message from error to warnings ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/63078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7e7923265c84999b97a075f0757e7a8d8963b2d Gerrit-Change-Number: 63078 Gerrit-PatchSet: 6 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: abandon

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coreboot-gerrit March 2022