coreboot-gerrit March 2022

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Change in coreboot[master]: soc/amd/sabrina: Add espi_switch_to_spi2_pads
by Felix Held (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63095 ) Change subject: soc/amd/sabrina: Add espi_switch_to_spi2_pads ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/sabrina/espi_util.c: https://review.coreboot.org/c/coreboot/+/63095/comment/d90a8535_ce64bfb4 PS4, Line 13: 2 > I copied the name from Cezanne. I agree though it is confusing... i'd prefer to have the name match the interface name of the soc over consistency with previous hardware generations -- To view, visit https://review.coreboot.org/c/coreboot/+/63095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96baf6b9c169ed61d221352b29ac676bca40da21 Gerrit-Change-Number: 63095 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 15:45:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Implement mb_set_up_early_espi
by Felix Held (Code Review) 28 Mar '22

28 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63094 ) Change subject: mb/google/skyrim: Implement mb_set_up_early_espi ...................................................................... mb/google/skyrim: Implement mb_set_up_early_espi This will setup the eSPI GPIOs in bootblock right before eSPI init. BUG=b:226635441 TEST=build skyrim Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I6ff32bf840aa4b757e98d876cbd4e2ba15a760da Reviewed-on: https://review.coreboot.org/c/coreboot/+/63094 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/skyrim/bootblock.c M src/mainboard/google/skyrim/variants/baseboard/gpio.c M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h 3 files changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/bootblock.c b/src/mainboard/google/skyrim/bootblock.c index 5a1c4da..c332aed 100644 --- a/src/mainboard/google/skyrim/bootblock.c +++ b/src/mainboard/google/skyrim/bootblock.c @@ -1,8 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/espi.h> #include <bootblock_common.h> #include <baseboard/variants.h> +void mb_set_up_early_espi(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + variant_espi_gpio_table(&gpios, &num_gpios); + gpio_configure_pads(gpios, num_gpios); +} + void bootblock_mainboard_early_init(void) { size_t num_gpios, override_num_gpios; diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index fd85b99..a262347 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -141,6 +141,23 @@ PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), }; +static const struct soc_amd_gpio espi_gpio_table[] = { + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* ESPI1_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* ESPI1_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + /* ESPI1_DATA2 */ + PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + /* ESPI1_DATA3 */ + PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), +}; + static const struct soc_amd_gpio tpm_gpio_table[] = { /* I2C3_SCL */ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), @@ -222,6 +239,12 @@ *gpio = sleep_gpio_table; } +__weak void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + *gpio = espi_gpio_table; +} + __weak void variant_tpm_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) { *size = ARRAY_SIZE(tpm_gpio_table); diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h index 64a414b..7289e10 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h @@ -37,6 +37,9 @@ /* This function provides GPIO settings before entering sleep. */ void variant_sleep_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); +/* This function provides GPIO settings for eSPI bus. */ +void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + /* This function provides GPIO settings for TPM i2c bus. */ void variant_tpm_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); -- To view, visit https://review.coreboot.org/c/coreboot/+/63094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff32bf840aa4b757e98d876cbd4e2ba15a760da Gerrit-Change-Number: 63094 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Implement mb_set_up_early_espi
by Felix Held (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63094 ) Change subject: mb/google/skyrim: Implement mb_set_up_early_espi ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff32bf840aa4b757e98d876cbd4e2ba15a760da Gerrit-Change-Number: 63094 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 15:44:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Swap eSPI_CS_L and SOC_DISABLE_DISP_BL
by Felix Held (Code Review) 28 Mar '22

28 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63093 ) Change subject: mb/google/skyrim: Swap eSPI_CS_L and SOC_DISABLE_DISP_BL ...................................................................... mb/google/skyrim: Swap eSPI_CS_L and SOC_DISABLE_DISP_BL The eSPI CS function only exists on AGPIO30. We will need to rework all boards to make eSPI function. I also fixed the comments on the other eSPI pins. BUG=b:226635441 TEST=Build skyrim Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ib03c0a7dcad31d10dd4bad0d10a0184ab84aef9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63093 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/skyrim/variants/baseboard/gpio.c 1 file changed, 10 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index d586405..fd85b99 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -46,7 +46,7 @@ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), /* WLAN_DISABLE */ PAD_GPO(GPIO_21, LOW), - /* ESPI_ALERT_D1 */ + /* ESPI_ALERT_L */ PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), /* AC_PRES */ PAD_NF(GPIO_23, AC_PRES, PULL_UP), @@ -60,8 +60,8 @@ /* GPIO_28: Not available */ /* EN_PP3300_TCHSCR */ PAD_GPO(GPIO_29, HIGH), - /* SOC_DISABLE_DISP_BL */ - PAD_GPO(GPIO_30, LOW), + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* Unused */ PAD_NC(GPIO_31), /* LPC_RST_L */ @@ -75,21 +75,21 @@ /* GPIO_43 - GPIO_66: Not available */ /* GPIO_67 */ PAD_GPI(GPIO_67, PULL_NONE), - /* SPI1_DATA2 */ + /* ESPI1_DATA2 */ PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), - /* SPI1_DATA3 */ + /* ESPI1_DATA3 */ PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), - /* ESPI_CS_L */ - PAD_NF(GPIO_74, SPI1_CS1_L, PULL_NONE), + /* SOC_DISABLE_DISP_BL */ + PAD_GPO(GPIO_74, LOW), /* TCHSCR_REPORT_EN */ PAD_GPO(GPIO_76, LOW), - /* SPI1_CLK */ + /* ESPI_CLK */ PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), /* EN_PP3300_CAM */ PAD_GPO(GPIO_78, HIGH), - /* SPI1_DATA1 */ + /* ESPI1_DATA1 */ PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), - /* SPI1_DATA0 */ + /* ESPI1_DATA0 */ PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), /* EC_SOC_INT_ODL */ PAD_GPI(GPIO_84, PULL_NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/63093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib03c0a7dcad31d10dd4bad0d10a0184ab84aef9a Gerrit-Change-Number: 63093 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Swap eSPI_CS_L and SOC_DISABLE_DISP_BL
by Felix Held (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63093 ) Change subject: mb/google/skyrim: Swap eSPI_CS_L and SOC_DISABLE_DISP_BL ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib03c0a7dcad31d10dd4bad0d10a0184ab84aef9a Gerrit-Change-Number: 63093 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 15:43:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge/acpi: Support setting PCI bars above 4G
by Felix Held (Code Review) 28 Mar '22

28 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51060 ) Change subject: nb/intel/sandybridge/acpi: Support setting PCI bars above 4G ...................................................................... nb/intel/sandybridge/acpi: Support setting PCI bars above 4G Although coreboot can allocate resources above 4G, Linux does not consider those allocation valid when there is no region above 4G in _CRS and disables the device. TESTED: x220 with and external GPU via the expresscard slot. Linux does not touch the BARs allocated above 4G. Change-Id: If1be9a2c1e03e5465fd3b164469511eca60edc5a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51060 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/acpi/hostbridge.asl M src/northbridge/intel/sandybridge/northbridge.c 2 files changed, 50 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 5421725..fa472b1 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -326,6 +326,12 @@ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,,, PM01) + // PCI Memory Region above 4G TOUUD -> 1 << cpu_addr_bits + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM02) + // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, @@ -333,6 +339,9 @@ 0x00005000,,, TPMR) }) +External (\A4GS, IntObj) +External (\A4GB, IntObj) + Method (_CRS, 0, Serialized) { // Find PCI resource area in MCRS @@ -359,5 +368,15 @@ PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1 PLEN = PMAX - PMIN + 1 + If (A4GS != 0) { + CreateQwordField(MCRS, ^PM02._MIN, MMIN) + CreateQwordField(MCRS, ^PM02._MAX, MMAX) + CreateQwordField(MCRS, ^PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + MLEN = \A4GS + MMIN = \A4GB + MMAX = MMIN + MLEN - 1 + } + Return (MCRS) } diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index fe769f9..1bc812a 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/cpu.h> #include <console/console.h> #include <acpi/acpi.h> +#include <acpi/acpigen.h> #include <commonlib/helpers.h> #include <device/pci_ops.h> #include <delay.h> @@ -82,6 +84,14 @@ } } +static uint64_t get_touud(const struct device *dev) +{ + uint64_t touud = pci_read_config32(dev, TOUUD + 4); + touud <<= 32; + touud |= pci_read_config32(dev, TOUUD); + return touud; +} + static void mc_read_resources(struct device *dev) { uint64_t tom, me_base, touud; @@ -123,9 +133,7 @@ */ /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config32(dev, TOUUD + 4); - touud <<= 32; - touud |= pci_read_config32(dev, TOUUD); + touud = get_touud(dev); /* Top of Lower Usable DRAM */ tolud = pci_read_config32(dev, TOLUD); @@ -372,13 +380,32 @@ pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); } +static void set_above_4g_pci(const struct device *dev) +{ + const uint64_t touud = get_touud(dev); + const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud; + + acpigen_write_scope("\\"); + acpigen_write_name_qword("A4GB", touud); + acpigen_write_name_qword("A4GS", len); + acpigen_pop_len(); + + printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", touud, len); +} + +static void mc_gen_ssdt(const struct device *dev) +{ + generate_cpu_entries(dev); + set_above_4g_pci(dev); +} + static struct device_operations mc_ops = { .read_resources = mc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .ops_pci = &pci_dev_ops_pci, - .acpi_fill_ssdt = generate_cpu_entries, + .acpi_fill_ssdt = mc_gen_ssdt, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/51060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1be9a2c1e03e5465fd3b164469511eca60edc5a Gerrit-Change-Number: 51060 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/sconfig: Fix for multidomain support sconfig/devicetree.cb
by Arthur Heymans (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Furquan Shaikh, Martin Roth, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51180 ) Change subject: util/sconfig: Fix for multidomain support sconfig/devicetree.cb ...................................................................... Patch Set 5: (1 comment) File util/sconfig/main.c: https://review.coreboot.org/c/coreboot/+/51180/comment/04ce601a_3e591e73 PS5, Line 1344: extern DEVTREE_CONST struct device *const __pci_%d_%02x_%d Does this make sense? You'd sort of expect this to be a PCI's BDF but that's not the case with the multidomain approach. Maybe only expose devices when the ptr->parent->dev->path_a == 0? -- To view, visit https://review.coreboot.org/c/coreboot/+/51180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd639d0cb3ed1a49ed7c7b1c77ac747ba6f77672 Gerrit-Change-Number: 51180 Gerrit-PatchSet: 5 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 15:27:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/sconfig: Fix for multidomain support sconfig/devicetree.cb
by Mariusz Szafrański (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Furquan Shaikh, Martin Roth, Jonathan Zhang, Paul Menzel, Angel Pons. Mariusz Szafrański has removed Michal Motyl from this change. ( https://review.coreboot.org/c/coreboot/+/51180 ) Change subject: util/sconfig: Fix for multidomain support sconfig/devicetree.cb ...................................................................... Removed reviewer Michal Motyl. -- To view, visit https://review.coreboot.org/c/coreboot/+/51180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd639d0cb3ed1a49ed7c7b1c77ac747ba6f77672 Gerrit-Change-Number: 51180 Gerrit-PatchSet: 5 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: util/sconfig: Fix for multidomain support sconfig/devicetree.cb
by Mariusz Szafrański (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Furquan Shaikh, Martin Roth, Jonathan Zhang, Paul Menzel, Angel Pons, Michal Motyl. Mariusz Szafrański has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51180 ) Change subject: util/sconfig: Fix for multidomain support sconfig/devicetree.cb ...................................................................... Patch Set 5: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51180/comment/8ee75a34_9546d1b7 PS3, Line 11: i.e. > Please adda blank line below. Done https://review.coreboot.org/c/coreboot/+/51180/comment/e2885646_ffc47114 PS3, Line 20: it`s > its Done https://review.coreboot.org/c/coreboot/+/51180/comment/c58dc98e_0d86d816 PS3, Line 20: Two domains (each with it`s own root PCI bus) and device with 00.0 > Please add a blank line above. Done https://review.coreboot.org/c/coreboot/+/51180/comment/c95ebbc7_b608944f PS3, Line 22: > Tested how? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd639d0cb3ed1a49ed7c7b1c77ac747ba6f77672 Gerrit-Change-Number: 51180 Gerrit-PatchSet: 5 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 15:15:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: util/sconfig: Fix for multidomain support sconfig/devicetree.cb
by build bot (Jenkins) (Code Review) 28 Mar '22

28 Mar '22

Attention is currently required from: Furquan Shaikh, Martin Roth, Jonathan Zhang, Angel Pons, Michal Motyl. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51180 ) Change subject: util/sconfig: Fix for multidomain support sconfig/devicetree.cb ...................................................................... Patch Set 5: Verified+1 (2 comments) File util/sconfig/main.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144875): https://review.coreboot.org/c/coreboot/+/51180/comment/e22e32aa_fead42ad PS5, Line 1350: fprintf(head, "extern DEVTREE_CONST void *const __pci_%d_%02x_%d_config;\n", line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144875): https://review.coreboot.org/c/coreboot/+/51180/comment/dbe59a04_e3c9b189 PS5, Line 1352: fprintf(fil, "DEVTREE_CONST void *const __pci_%d_%02x_%d_config = &%s_info_%d;\n", line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/51180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd639d0cb3ed1a49ed7c7b1c77ac747ba6f77672 Gerrit-Change-Number: 51180 Gerrit-PatchSet: 5 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Comment-Date: Mon, 28 Mar 2022 15:08:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2022